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R&D Electronics (Pty) Ltd 



QBX-TMR 

MULTI-FUNCTION TIMING 
CONTROLLER 



QBX-TMR 



Product:- QBX-TMR 
Product Number:- 1005 
Manual Number:- 1005-01 



7 



I Chapter 



All 



Rev I Note I 



I I 
1.01 1 I 
I I 
I 



I 

I I 
I I 

Notes : - 

1. Original Document 



All rights to this publication are reserved. No part of it may be 
copied or reproduced in any form without prior written consent. 
Except where noted copyright vests with Quantum Electronics. 



The information 
notice . 



mation 
(Pty) 



in this document is subject to change 



i 



wi thout 

Whilst every effort is made to ensure that the infor- 
contained in this document is correct, R&D Electronics 
td assumes no respo 5 i bi 1 i ty for any errors that may occur. 



R&D Electronics (Pty) Ltd assumes no responsibility for the use 



o f any 



circuitry other than the circuitry embodied in a product 



manufactured by R&D Electronics (Pty) Ltd, 

R & D Electronics (Pty) Ltd makes no warranty on the 
this product for a specific purpose. 



of 



iSBX, iSBC, Multibus, 
Intel Corporation. 



MULTI MODULE , and Intel are trademarks of 



All products are warranted against defects in material and work- 
manship under normal and proper use and in their original and 
unmodified condition. If found defective by R & D Electronics 
(Pty) Ltd within the terms of this warranty, the sole obligation 
of R & D Electronics (Pty) Ltd shall be to repair or replace (at 
the option of R & D Electronics (Pty) Ltd the defective product. 
The warranty period is 90 days from delivery of the product. 



(c) Copyright October 1982 



Quantum Electronics, 

c/o R&D Electronics (Pty) Ltd, 

P.O. Box 61903, 

Marshalltown 2107, 

Johannesburg, South Africa. 

Telex: 8-3046 Phone: 834-1204 



Rev : 1 . 



QBX-TMR 



CONTENTS 



CHAPTER 1 
GENERAL 

Introduction 

Description 

Equipment supplied 
Specifications .... 



PAGE 



CHAPTER 3 
PROGRAMMING IN 

Introduct ion 
Overview 

Functional Summary 
Notes 



........... 



..... 



CHAPTER 
SERVICE 
I nt r oduct ion 
Parts List 
Schematics 



INFORMATION 



• •••••••• 



APPENDIX 

Appendix A 
Am9513 Data Sheet 



Rev : 1 . 



3, 
3. 
3 
3, 



5, 
5, 
5, 



A. 1 



C. 1 



PAGE 

CHAPTER 2 

PRINCIPLE OF OPERATION 

Introduction 2.1 

QBX Bus Interface 2.1 

Am9513 STC 2.1 

Clock Reference 2.1 

Inputs 2.2 

Source Inputs 2.2 

Gates 2.2 

Auxiliary Gates 2.2 

Outputs 2.2 

Fout 2.3 

I nter rupt 2.3 

Jumper Pads 2.4 

Edge Connector 2.4 



CHAPTER 4 

PREPARATION FOR USE 

Introduction 4.1 

Unpacking 4.1 

Configuration 4.1 

Mounting 4.1 

Edge Connector 4.1 



Appendix B 

Applications B.l 

General 

Frequency Counter 

Analogue to Digital Converter 



QBX-TMR 



TABLES 

Table 



2 
2 
2 
5 
5 
5 
5 



FIGURES 

Figure 

2.1 
5.1 
5 .2 



Title Page 

Valid Addresses and their Functions 2.1 

Jumper Pad Functions 2.4 

Edge Connector Pinout 2.5 

Source Inputs 5.3 

Gate Inputs 5.3 

Auxiliary Gate Inputs 5.3 

Outputs 5.3 

Title Page 

Potential Supresso: Diode Problem 2.3 

QBX-TMR Schematic Diagram 5.2 

U3 pinout ••••••••»••••»•••••••••••••••••••«•••••• 5.3 



Rev : 1 . 



C. 2 



Introduction 



CHAPTER 1 
GENERAL 



The QBX-TMR is one of l\ growing range of iSBX bus compatible 
boards manufactured by R&D Electronics. These boards are 
designed to increase the number of functions in a Multibus system 
without having to resort to a full Multibus card to achieve that 
function. This document provides all the information required to 
use the QBX-TMR. 



Description 



The Am9513 
advanced of 
i ndependent 
multitude of 



System Timirg Contoller (STC) is one of the most 
its type on t.he market. It provides the user with 5 
16 bit counters which can be configured in a 
modes. The QBX-TMR is designed to provide Multibus 



users with this flexibilty on a single SBX card. The capabilties 
include for each counter, up or down counting, binary or BCD, 
programmable counting sources including external oscillator, 
external signals, or even a previous counter. There is a Time-of- 
Day option with Alarm comparators for this or other functions. 
The counter output polarities are programmable and coupled with 
gating the counters may be controlled by external signals. 

The QBX-TMR enhances these 1 features by providing an accurate time 
reference for the Am9513. In addition counter and gate inputs are 
protected against over vcltage while the outputs are buffered by 
Darlington drivers to allow medium current and medium voltage 
interface. Interrupt cafabilty is also provided for the host 
compute r . 



Equipment Suppl ied 



The QBX-TMR is shipped in a padded package. Included in 



packet 



board on a host SBC type board. 



are 2 plastic screws and a plastic spacer to mount 



the 
the 



Rev : 1 . 



1.1 



QBX-TMR Chapter 1: General 



s P ecif 



cations 



Access Time: 
STC read - 160nS 
STC write - 150nS 
Buffer read - 52nS 



Counting Rate: 

On MCLK 13.793 MHz 

On SRC1-5 and Gate 1-5 



6.896 MHz 



Addressing Range: 

The QBX-TMR is compatible with any board that supports the Intel 
iSBX bus. The addressing range of the QBX-TMR is derived from 
this host board. 



I nte r f ace : 

System Bus Compatible witi the SBX bus specifications. See Intel 

publication 142686-001. 
QBX-TMR inputs 

Input low voltage: Min (Vss-0.5) V Max 0.8 V 

Input high voltage: Min 2.3V Max Clamped to 4.7V by zeners 

QBX-TMR outputs 

Maximum output voltage 5i3V 

Output Current Sink 200mA per device all devices on 100% duty 
cycle. 

For more detailed spec i -cations see data sheet on ULN2003A 
(Sprague) or MC1413 (Motorola), or 9667 (Fairchild) or SN75478 
(T.I .) . 

Interface connectors: 

25/50 way, 0.1 inch spacing, compatible with Robinson-Nugent IDE- 
50 or similar. 

Power Requirements: 
+5V +/-5% @402mA 

Envi ronment : 

Operating Temperature 0-55 degrees Celsius, humidity to 90% non- 
condensing . 



Size: 
Width 
Length 
Thickness 
Weight 



72.4 mm (2.85 in) 
94.0 mm (3.70 in) 
20.6 mm (0.81 in) 



Rev: 1 .0 



1.2 



QBX-TMR Chapter 2: Principle of Operation 



CHAPTER 2 
PRINCIPLE OF OPERAT: 

I ntroduction 



This chapter describes the hardware operation of the QBX-TMR. 
Detailed description of the Am9513 capabilties are described in 
the appendix. 

QBX Bus Interface 



Detailed description of tne SBX bus is given in the Intel public- 
ation 142686-001. Users are referred to this document for a 
clearer understanding oE its operation. The QBX-TMR uses the 
following signals:- MD0-MD7 , MA0 , CS0/, CS1/, IOWRT/, IORD/, 
MCLK, MINTR0, MINTRl , OPT0 , 0PT1 , +12V and of course +5V , gnd 
and MPST/. 

Am9513 STC 



Interface to the STC is via several 8 bit registers. The host 
data bus is connected to ;he STC data bus and these registers are 
accessed by means of a read or write command being active simul- 
taneously with CS0/. The register being accessed is determined by 
the state of the MA0 line. See table 2.1 for the different 
f unctions . 

The STC is capable of 16 or 8 bit parallel operation. 



TMR it 



In the QBX- 



can only be used for 8 bit parallel operation. 



T 



ABCD0XX0 | 


8 


1 


1 Read 


Data Port 


I ABCD0XX0 | 




1 1 


I Write 


Data Port I 


I ABCD0XX1 | 


8 


1 


I Read 


Control Port I 


1 ABCD0xxl | 




1 8 


1 Write 


Control Port 1 


1 ABCDlxxx | 


8 


1 


I Read 


Buffer | 


ABCD are bit 


vali 


les that 


are determined by the 


host board. 










x is a don 1 t 


care 


; cond i t ion , i . e 


. 1 or . 



8 - active 



Table 2.1 

Valid Addresses and their Functions 



Clock Reference 



The clock used to provide internal timing functions is derived 
from the MCLK signal. The MCLK signal is divided by 2 (U5/11) and 
fed to the input of the ETC. Whilst this signal is nominally 10 
MHz the user should check this value on the host board being used 
if this signal is to be used to determine accurate timing values. 



If for 
he may 
and connected 



some reason the user wishes to provide his own time source 
disable this clock by breaking the link just to the side 
to R3. Remove R4 and install R3 and C2. Note that 



Rev : 1 . 



QBX-TMR Chapter 2: Principle of Operation 



the 
wide 
may be 



frequency of oscillation in this configuration is subject to 
temperature and power supply variations. Alternatively R3 
replaced with a coil. 



Inputs 



Source 



Inputs 



The STC has 5 inputs that may be routed via software to any or 
all of the 5 counters. These inputs are entitled SOURCE 1 to 
SOURCE 5. These inputs are buffered on the STC by a Schmitt 
Trigger and so can handle slow rise and fall times. These inputs 
are protected from overvoltage by a resistor-zener diode network, 
If the source does not exceed Vcc then the zener diode can be 
removed to reduce the current drive requirements. The resistors 
are either discreet or par: of a resistor array RN1. This array 
is shared with some gate inputs. If it is a requirement to have 
different resistor values :hen the array (and the discreet resis- 
tors Rl and R2) may be removed and by using a DIL component 
header these values may be individually set. 

Gates 

The STC has 5 inputs entitled GATE 1 to GATE 5. These inputs may 
be used to control when the counters change or may also be used 
as a source for any or all of the counters. These inputs are also 
buffered by a Schmitt Trigger. In a similar fashion to the source 
inputs \ these gate inputs are protected by a resistor-zener diode 
network. In addition each gate has a jumper pad associated with 
it (see table 2.2) which mciy be used to trigger an interrupt (see 
the section in this chapter on interrupts). 

Auxiliary Gates 



In addition to the above gates the STC also allows for 5 
additional gates that may perform as gates only. These inputs are 
NOT protected against overvoltage, and only have a pullup to Vcc. 

Outputs 



Each counter has an output associated with it, entitled OUT 1 to 
OUT 5. These outputs drive the inputs of a Darlington driver. All 
these drivers are included in a single package, the MC1413. The 
output of this device is inverted with relation to the input. It 
is open collector and is capable of being pulled up to 50V. In 
the ON condition it is also capable of sinking medium currents 
and this value will vary depending of the duty cycle and how many 
are drivers are on. However the basic minimum (all on, 100% duty 
cycle) is 200mA per driver. 

On board pull up resistors are provided in a DIL resistor array. 
The voltage side of the resitors are commoned and brought out to 
a jumper pad W17. This may oe jumpered to W14 (Vcc), or W16 which 
allows any voltage to be brought in from the edge connector. 
(System +12V is also available at the edge connector.) If differ- 
ent values of resistors are required the array RN2 may be 



Rev : 1 . 



2 ,2 



QBX-TMR Chapter 2: Principle of Operation 



replaced by a DIL component header with individual resistors. In 
addition, if each output is to be pulled up to a different value 
then the resistors may be removed .Alternatively by cutting the 
track that joins pins 16 to 11 and providing the required pullup 
voltages at the respective pins (see table 2.3) on the edge 
connector the result may be achieved. 

Inherent to the MC1413 (J3) on each output is an internal sup- 
ression diode that may be used to supress reverse EMF on induc- 
tive loads. The cathodes of these diodes (see sheet 2 of the 
schematic diagram Chapter 5) are commoned and brought to a jumper 
pad (W15) and out to the edge connector. When earthed the outputs 
are turned on and so this feature may be used for a test feature. 
If this is to be used for suppression be sure that the voltage at 
this point is the highest potential in the circuit associated 
with the outputs as the diode may turn on as shown in figure 2.1. 
Each output has a jumper pad (see table 2.2) associated with it 
to use as a link to generate an interrupt. 

Since these outputs, under certain circumstances, may be set or 
reset at will, under those circumstances an output may be used as 
a normal single bit drive:. 



Fout 



The STC 
an output 

I nte r rupt 



also provides a periodic output known as Fout which has 
driver identica:. to those mentioned in "Outputs" above. 



Both interrupt lines MINT0 and MINT1 are supported, whilst 
additional interrupt facilities may be created by using the OPT0 
and 0PT1 lines. MINT0, MINTl , and OPT0 are buffered. Any one of 
the above GATE or OUT functions may be used to generate and 
interrupt by linking the respective jumper pads. The output 0PT1 
is not buffered and should be used with caution if the output is 
used to drive U2, see the following paragraph. 

When a GATE input goes inactive (low in this case) a counter may 
stop counting and the system may want to read the count at this 
time. An interrupt may be generated using U6 and Ul . Any output 
or GATE input jumpered tc the inputs of Ul . When any input goes 
low the output (Ul/13) goes high it clocks a high onto the Q 
output of the D-type flip-flop. This output (W24) may be used to 
generate an interrupt. Reading from location ABCDlxxx as from 
table 2.1 clears this interrupt. It also allows the processor to 
see the cause of the interrupt, as the buffer U2 is enabled on to 
the data bus. Even if more than one signal is low simultaneously 
only one interrupt is generated. The software should cater to 
test for more that one cause of the interrupt should this arise. 



if V1>V2+0.6V 
then diode is 
biassed on 



VI \ — T 



v2 ' — KF 




Figure 2.1 
Potential Supressor Diode Problem 



Rev : 1 . 



2.3 



QBX-TMR Chapter 2: Principle of Operation 



J umpe r Pads 



On the 



QBX-TMR the letter W is omitted from all the jumper pads, 



Pad Number 


Function 


Wl 


GATE 1 


input 




I W2 


1 GATE 2 


input 




W3 


1 GATE 3 


input 




1 W4 


1 GATE 4 


input 




1 W5 


I GATE 5 


input 




W6 


1 Bit 7 


NAND gate 


input I 


W7 


1 Bit 


NAND gate 


input 1 


WR 


I Bit 1 


NAND gate 


input I 




I Bit 2 


NAND gate 


input I 


Wl 


1 Bit 3 


NAND gate 


input I 


| ri X _L 


I Bit 4 


NAND gate 


input I 


Wl 2 


| Bit 5 


NAND gate 


input I 


W13 


1 Bit 6 


NAND gate 


input I 


1 W14 


1 +5V 






i W15 


I common 


cathode 






1 supression diodes 




Wl 6 


I Auxiliary pullup 






1 voltage input 




W17 


1 Resistor Array RN2 




1 common 






W18 


1 OUT 5 






1 W19 


1 OUT 4 






1 W20 


1 OUT 3 






1 W21 


1 Fout 






1 W22 


1 OUT 1 






1 W23 


1 OUT 2 






W24 


I output 


interrupt 






1 flip flop 




W25 


1 0PT1 






1 W26 


1 OPT0 






1 W27 


I MINT0 






1 W28 


I MINT1 







Table 2.2 
Pad Functions 



Edge Connector 



The following table provides the functional pinout of the edge 
connector, 



Rev: 1 .1 



2.4 



QBX-TMR Chapter 2: Princ:.ple of Operation 



I fin 


I Function 




- 


1 
J- 


nc 








1 9 
Z 


1 4.1 9ir 

T 1 Z V 








1 T 
1 J 


nc 








1 A 


OUT!/ 








1 c; 
O 


I supply 


side 


PU J. J. U JJ 


dutm / 

uu 1 1/ 1 


1 t) 


| UUli./ 








7 


1 supply 


side 


Dll 1 1 11D 

K-" -I. _L <w* 


0UT2/ 1 


1 Q 

o 


I 0UT3/ 








Q 

1 7 


1 supply 


side 


pullup 


0UT3/ 


1 10 


I Fout/ 










I supply 


side 


pullup 


Fout/ 


12 


OUTS/ 








1 1 ~\ 


j supply 


side 


pullup 


0UT5/ 


14 


OUT'? / 








i J- j 


I supply 


side 


pullup 


0UT4/ 


1 16 

I X v 


1 nc 








1 1 7 


| auxiliary pullup supply 


1 ft 
1 J- o 


I auxiliary gate 1 




I 1 Q 


Vcc 








1 Z Id 


I auxiliary gate 2 




9 1 

1 z X 


coramor 


cathode supression diode 


1 9 9 
1 Z Z 


1 auxiliary gate 3 




1 Z O 


nc 








1 9 A 


I auxiliary gate 4 




9 ^ 

1 Z D 


nc 








1 9 £ 
1 Z O 


I auxiliary gate 5 




1 9 7 
Z / 


gnd 








1 28 


nc 








9 Q 
z y 


1 gnd 








1 J 


I nc 








1 "3. 1 
1 -3 ± 


1 gnd 








1 "3 9 
1 O z 


| nc 








1 1 1 
1 J J 


1 gnd 








1 "3 A 


I nc 








1 "3 


1 gnd 








1 -3 D 


I nc 








"3 7 


gnd 








1 "3 ft 


nc 








"3Q 


1 gnd 








1 4 01 
1 1 10 


1 nc 








! A 1 


1 SOURCE 


1 






1 42 


1 GATE 1 








43 


1 SOURCE 


2 






I 44 


j GATE 2 








1 45 


1 SOURCE 


3 






I 46 


1 GATE 3 








1 47 


1 S0URC3 


4 






1 48 


1 GATE 1 








1 49 


I S0URC3 


5 






1 50 


1 GATE 5 









Table 2.3 
Edge Connector Pinout 



Rev: 1 .0 



2.5 



QBX-TMR Chapter 3: Programming Information 



Introduction 



CHAPTER 3 
PROGRAMMING INFORMATION 



All the information required to programme the Am9513 STC is 
presented in appendix A as part of the Am9513 Data Sheet. This 
chapter will provide an overview and functional summary. 

Overview 



Counting events and timing intervals are fundamental to a large 
portion of microcomputer projects. The flexibilty of the STC 
allows many combinations of these requirements and is presented 
for the Multibus user as a QBX module. 

Time related functions can be broken into several categories such 
as frequency generation, waveform duty cycle control, event 
counting, interval measurement, precise periodic interrupts, time 
of day accumulation, delctys, and gap detection. When several of 
these functions must be attained simultaneously problems can 
arise on processor throughput if the processor is performing 
these without the aid of peripheral support devices. 



Use of 



counters can be divided into two categories: 



(a) Count Accumulation. 

The counter simply accumulates (either by incrementing or decre- 
menting) events occurring at its input. At any stage the prog- 
ramme may need the value of this counter to use in furthering 
processing. The value of this count may need to be modified 
(perhaps reset to a starting value). The periods of counting may 
need to be halted, in both hardware and software. 



It is 
purely 



the count that is of interest, 
incidental . 



and a count of zero is 



(b) Frequency Division 

In this instance the output from the counter is of interest. The 
actual counter value instantaneously is incidental. An output 
signal is used to indicate the zero state of the counter, and by 
programming the value of the counter combined with the incoming 
signal generate different frequencies at the output. Extra 
conditions may allow different output waveforms under software or 
hardware control. 

The STC allows for all of the above with some of the processes 
occuring simultaneously vvithin the device. The QBX-TMR enhances 
the device by providing the inputs with overvoltage protection 
and providing the outputs with high voltage, medium current drive 
capabilties. In addition there are interrupt conditons to match 
the requirements of the host computer. 

Functional Summary 

The capabilties of the 9513 are listed in point form to allow the 



Rev:1.0 



3.1 



QBX-TMR Chapter 3: Programming Information 



user to skim through. 



ivb 
v) 
vi) 
vi i ) 



1. 5 independent 16 bit counters. 

2. Up/Down counting 

3. Binary/BCD counting. 

4. Time of Day option on counters 1 and 2. 

5. Alarm comparators on counters 1 & 2. 

6. Complex duty cycle outputs e.g. FSK generation. 

7. Counters may be internally concatenated with adjacent counter 
to extend the counting range. 

8. Selectable divided output of external clock reference. 

9. Each counter may have as its source one of 16 inputs: 

i) previous counter 

ii) SOURCE 1-5 

iii) GATE 1-5 
External clock reference 
(iv) divided by L0 or 16 
(iv) divided by L00 or 256 
(iv) divided by L000 or 4096 

viii) (iv) divided by L0000 or 65536 

10. The input polarities of the above signals is programmable. 

11. Each counter may be controlled by its associated gate and the 
gates adjacent to it. In the case of its associated gate the 
gate may be active low or high, or positve or negative edge 
sensitive. 

12. Retriggering capability. 

13. Each counter may be controlled by its associated auxiliary 
gate . 

14. The output can be programmed for active high or low. 

15. Monostable or continuous ouptuts. 

16. The output in certain conditions can be set or reset by 
software control. 

17. Any counter can be stepped under software instruction. 

18. Simultaneous start and saving of up to all 5 counters. 

19. Data Pointer Sequencing. 

20. Random access to any register for write and read. 
Notes 

Use of the QBX-TMR has shown that some points need to be stressed 
or clarified. 

1. The users attention is drawn to the section entitled "Prefetch 
Circuit" in appendix A. Further if the QBX-TMR is configured 
as memory mapped I/O beware of instructions that could 
programme two bytes at a time (for instance SHLD) as this may 
violate the times TRHRL or TWHWL . (A QBX board may be memory 
mapped by using anoiher board manufactured by R & D 
Electronics entitled the QBC-QBX. This board allows a Mutlibus 
interface to 4 QBX boards with memory or I/O mapped I/O.) 

2. Never configure the Am9!il3 for 16 bit parallel operation. 

3. In order to set and clear outputs the counter mode bits 
CM2, CM1, CM0 must be set to 010. 



Portions of the above text are summarised from an AMD publication- "Am9513 
System Timing Controller Detailed Functional Description" by Joseph H.Kroeger 



Rev : 1 . ! 



■1.2 



QBX-TMR Chapter 4: Preparation for Use 



CHAPTER 4 
PREPARATION FOR USE 



I ntroduct ion 



This chapter provides information on the installation of the QBX- 
TMR on a host SBC board. 

Unpack ing 



The QBX-TMR is shipped in a padded packet together with 1 plastic 
spacer and 2 plastic screws. 

On receipt of the packcige inspect immediately for signs of 
damage, water or any other signs of mishandling. If there are any 
of these signs contact your carrier or his agent, or the local 



Conf iguration 



R&D Electronics repres 
please 



retain the packagirg. 



entative. If you do open the package, 



Configure the jumper ccnnections as required. This may be 
attained by fitting wire wrap posts to the pads and then wire- 
wrapping these or by soldering directly to the board. 



Mounting 



iSBX 
host 
only 

and 



The QBX-TMR will mount on any SBC computer that allows an 
board. Affix the spacer with one of the screws to the 
board. Mount the spacer in the hole corresponding to the 
mounting hole on the QBX board. 

The QBX-TMR should now be mounted on the mating connector 
affixed to the host board with the remaining screw. 

When a QBX card is mounted on a host card, the resulting 
structure occupies an additional card slot above the SBC card. 
Bear this in mind when you allocate slots in a cardframe. 

Edge Connector 



Mate the edge connector to the QBX board. This connector (if 



needed) 
Several 



a ribbon cable to screw terminals. 



Rev: 1 .1 



can be hand soldered or be of the ribbon cable variety, 
manufacturers (sucn as Electro-Phonix) make adaptors from 



4.1 



QBX-TMR Chapter 5: Servic 



I ntroduction 



This chapter provides a pc 
QBC-TMR. 

Parts List 



Semiconductors : 



CHAPTER 5 
SERVICE 



rts list and a schematic diagram of the 



Ul 
U2 
U3 
U4 
U5 
U6 



Dl-10 



itors ; 



Capaci 
CI ,3 



Resistors 
RN1 ,2 
RN3 ,4 

Rl ,2 
R4 ,6-8 

R5 



Connector : 



Unused 

R3 

C2 



CMOS 8 input NAND gate 
octal buffer 
darlington drivers 
System Timing Controller 
dual D-type flip-flop 
quad 2 input OR gate 



400 mW zener diodes 



ceramic 



DIL resistor array Epitek 6.8K 



SIL resistor an 

1/4W 5% 
1/4W 5% 
1/4W 5% 



ay Epitek 4.7K 



Viking 36 way SEiX 
Parts : 



MC14068 

74LS245 

MC1413 

Am9513 

74LS74A 

74LS32 



4V7 

. 01uF 



1608-683-G 
L807-472-G 

6.8 Kohm 
470 ohm 
4.7 Kohm 



LMP01KH18A01 



Rev: 1 .0 



5.1 



m> — . 
gs> — ■ 

l~4^> 



'Table 5. 1 



see 

iTable5.2 



— D>39 
— P>37 
-£>35 
H>"33 
H>3I 
— 1>29 
— D>27 




t> edge connector 
O Q6X connector 

/[\ not suppl ied 



QBX-TMR 
Sheet I of 2 
1005-02 



QBX-TMR Chapter 5: Service 



Function 


a 


Zb 


I Rc 


d 


e 


f 


I SOURCE 1 


33 


D2 


I R2 






141 I 


1 SOURCE 2 


32 


D3 


1 Rl 






1 43 I 


1 SOURCE 3 


31 


D4 


I RN1 


1 


1 16 


1 45 | 


1 SOURCE 4 


30 


D5 


1 RN1 


2 


1 15 


1 47 I 


1 SOURCE 5 


29 


Dl 


1 RN1 


3 


1 14 


1 49 I 



Table 5.1 
Source Inputs 



1 Function 


g I 


Zh 


1 Wi 




aa 


ab 


k 


1 GATE 1 


4 I 


D6 


1 Wl 


RNl 


4 


13 


42 I 


1 GATE 2 


39 1 


D7 


I W2 


RN1 


5 


12 


44 | 


1 GATE 3 


36 I 


D8 


1 W3 


RNl 


6 


11 


46 1 


1 GATE 4 


35 1 


D9 


[ W4 


RNl 


7 


10 


48 1 


1 GATE 5 


34 | 


D10 


1 W5 


RNl 


8 


9 


50 | 



Table 5.2 
Gate Inputs 



Function 


1 m 


Rn 


o 


1 P 1 


Aux. GATE 


1 


1 20 


1 RN4 | 


8 


1 18 | 


I Aux. GATE 


2 


1 22 


1 RN4 | 


7 


1 20 I 


I Aux. GATE 


3 


1 23 


I RN4 | 


6 


1 22 | 


1 Aux. GATE 


4 


1 24 


I RN4 | 


5 


1 24 | 


1 Aux. GATE 


5 


1 25 


I RN4 | 


4 


1 26 I 



Table 5.3 
Auxiliary Gate Inputs 



Functl 


.on 




r 




1 Rt | 


u 


V 


1 W 


X 


1 Wy_ I 


Foul 




r-H 


3 


1 li 


1 RN2 I 


3 


1 14 


1 11 


1 10 


W21 I 


1 OUT 


1 


3 


6 


I M 


1 RN2 | 


6 


1 11 


1 5 


1 4 


W22 | 


1 OUT 


2 


2 


5 


1 12 


1 RN2 | 


5 


1 12 


1 7 


1 6 


W23 I 


1 OUT 


3 


40 


4 


1 13 


I RN2 | 


4 


1 13 


1 9 


1 8 


W20 I 


1 OUT 


4 


38 


1 


1 111 


I RN2 | 


1 


1 16 


1 15 


1 14 


W19 I 


1 OUT 


5 


37 


2 


1 15 


1 RN2 | 


2 


1 15 


1 13 


1 12 


W18 | 



E- 
E- 
B- 
E- 
E- 
Er 



a 



Table 5.4 
Outputs 



Figure 5.2 
Pinout of U3 



QBX-TMR 

Sheet 2 of 2 
1005-02 



Rev 1.0 



5.3 



QBX-MSP Appendix A: Am9513 Data Sheet 



APPENDIX A 
Am9513 DATA SHEET 



The following pages are extracted from the Am9513 data sheet, 



Copyright (c) 1980 Advanced Micro Devices, Inc. 
Reproduced with permission of copyright owner. 
All rights reserved. 



Rev: 1 .0 



A.l 



Am9513 



OATt 1-4 - 



GENERAL BLOCK DIAGRAM 

t 



» 



* BIT 

«HKTIP 



and HUM 



|_ powtn on | 



COUKTTH 1 lOOtC WKXW 



COUNT!* 4 LOOK cnouf 



I LOOK owou* 



COONTEH 2 LOCUC OMOUP 



Figure 2. 



GATE - 
F«EQ - 



> 

I 



LOGIC 



counter 
look: 



i«-BfT LOaO "CGiiTf « 



i *-t».i WOLD WCGJSTEH 



HS-B/T cO«"«ATOn 



j*OSl- 



Figure 3. Counter Logic Groups 1 and 2. 



GATI - 
fBEQ - 



COONTF* 

coNinoc 
lock: 



I IfrBfl LOAD MCJSTEA I 



Figure 4. Counter Logic Groups 3, 4 and 5. 



INTERFACE SIGNAL DESCRIPTION 

Figure 5 summarizes the interlace signals and their abbreviations 
lor the STC. Figure 1 shows the signal pin assignments for the 
standard 40-pin dual in-line package. 



VCC: +5 volt power supply 



VSS: Ground 



FOUT (Frequency Out, Output) 

The FOUT output is derived trom a 4-bit counter that may be 
programmed to divide its input by any integer value from 1 
through 16 inclusive. The input to the counter is selected from any 
of 15 sources, including the internal scaled oscillator frequencies. 
FOUT may be gated on and off under software control and when 
off will exhibit a low impedance to ground. Control over the 
various FOUT options resides in the Master Mode register. After 
power-up, FOUT provides a frequency that is 1/16 that of the 
oscillator. 



XI. X2 (Crystal) 

XI and X2 are the connections for an external crystal used to 
determine the frequency of the internal oscillator. The crystal 
should be a parallel-resonant, fundamental-mode type. An RC or 
LC or other reactive network may be used instead of a crystal. For 
driving from an external frequency source. X1 snould be left open 
and X2 should be connected to a TTL source and a pull-up 
resistor. 



GATE1-GATE5 (Gate, Inputs) 

The Gate inputs may be used to control the operations of indi- 
vidual counters by determining when counting may proceed. The 
same Gate input may control up to three counters. Gate pins may 
also be selected as count sources for any of the counters and for 
the FOUT divider. The active polarity for a selected Gate input is 
programmed at each counter. Gating function options allow 
level- sensitive gating or edge-initiated gating. Other gating 




Am9513 



CONTROL POHT REGISTERS 

The STC is addressed by the external system as only two loca- 
tions: a Control port and a Data port. Transfers at the Control port 
(C/D = High) allow direct access to the command register when 
writing and the status register when reading. Ail other available 
internal locations are accessed (or both reading and writing via 
the Data port (C/D * Low). Data port transfers are executed to 
and from the location currently addressed by the Data Pointer 
register. Options available in the Master Mode register and the 
Data Pointer control structure allow several types ot transfer 
sequencing to be used. See Figure 7. 
Transfers to and from the control port are always 8 bits wide. Each 
access to the Control port will transfer data between the Com- 
mand register (writes) or Status register (reads) and Data Bus 
pins DB0-DB7, regardless of whether the Am95l3 is in 8- or 16-bit 
bus mode. When the Am9513 is in 8-bit bus mode, Data Bus pins 
DB13-DB15 should be held at a logic high whenever CS and WR 
are both active. 

Command Register 

The Command register provides direct control over each of the 
five general counters and controls access through the Data port 
by allowing the user to update the Data Pointer register. The 
"Command Description" section of this data sheet explains the 
detailed operation of each command. A summary of all com- 
mands appears in Figure 21 . Six of ihe command types are used 
for direct software control of the counting process. Each of Ihese 

aiA vu;n" iai iuj 'ia» >o a -i-uh -J nc"_i. w r a ui icai -ocicoi iqjihui i, 

each bit in the S fie'd corresponds to one of the five general 
counters (S1 = Counter 1 , S2 = Counter 2, etc.). When an S bit is 
a one. the specified operation is performed on the counter so 
designated; when an S bit is a zero, no operation occurs for the 
corresponding counter. 

Data Pointer Register 

The 6-bit Data Pointer register is loaded by issuing the appro- 
priate command through the control port to the Command regis- 
ter. As shown in Figure 7, the contents of the Data Pointer register 
are used to control the Data Port multiplexer, selecting whk:h 
internal register is to be accessible through the Data Port. 



The Dala Pointer consists of a 3-bi! Group Poinlor. a 2-bit Ele- 
ment Pointer and a I -bit Byte Pointer, depicted in Figure 8. The 
Byte Pointer bit indicates which byte of a 16-bit register is to be 
transferred on the next access through the data port. Whenever 
the Data Pointer is loaded, the Byte Pointer bii is sel to one, 
indicating a least-significant byte is expected. The Byte Pointer * 
toggles following each 8-bit data transfer with an 8-bit. data bus 
(MM13 = 0). or it afways.remains set with the 16-bit data bus 
option (MM13 m 1). The Clement and Group pointers are used to 
select which internal register is to be accessible through the Data 
Port. Although the contents of the Element and Group Pointer in 
the Data Pointer register cannot be read by the host processor, 
the Byte Pointer is available as a bit in the Status register. 
Random access to any available interna! data location can be 
accomplished by simply loading the Data Pointer using the com- 
mand shown in Figure 9 and then initiating a data read or data 
write. This procedure can be used at any time, regardless of the 
setting of the Data Pointer Control bit (MM14). When the 8-bit data 
bus configuration is being used (MM13 = 0), two bytes of data 
would normally be transferred following the issuing of the "Load 
Data Pointer" command. 

To permit the host processor to rapidly access the various internal 
registers, automatic sequencing of the Data Pointer is provided. 
Sequencing is enabled by clearing Master Mode bit 14 (MM14) to 
zero. As shown in Figure 10, several types of sequencing are 
available depending on the data bus width being used and the 
initial Data Pointer value entered by command. 
When El = Oor E2 = 0andG4. G2.G1 point to a Counter Group, 
the Data Pointer will proceed through the Element^ cycle. The 
Element field will automatically sequence through the three val- 
ues 00, 01 and 10 starling with the value entered. When the 
transition from 10 to 00 occurs, the Group field will also be 
incremented by one. Note that the Element field in this case does 
not sequence to a value of 11. The Group field circulates only 
within the five Counter Group codes. 

If E2, E1 = 11 and a Counter Group is selected, then only the 
Group field is sequenced. This is the Hold cycle. It allows the Hold 
registers to be sequentially/accessed while bypassing the Mode 
and Load registers. The third type of sequencing is the Control 



Figure 7. Am9513 Register Access. 



Am9513 



G4 



G2 


G1 


[ E2 


,.E1 


BP 



Byte Pointer 

tn^Most significant Byte TraTsteTe^ nTrf 



■ Group Pointer ' — 

000 = Illegal 

001 » Counter Group 1 
010 = Counter Group 2 
011= Counter Group 3 

100 = Counter Group 4 

101 = Counter Group 5 
110 = Illegal 

111= Control Group — 



Element Pointer 

(00 - Mode Register I 
01 = Load Register 
10 = Hold Register J 
11 - Hold Register/Hold Cycle Increment 



Element Cycle 
Increment 



00 = Alarm Register 1 

01 = Alarm Register 2 

10 - Master Mode Register 

1 1 = Status Register/No Increment 



Control Cycle 
Increment 



Figure 8. Data Pointer Register. 



cycle. IIG4,G2, G1 = 111 and E2, E1 j* 11, the Element Pointer 

'.•.-it: tc ■ i u i i. ii . i . »» t^.i^s,;. mm »=luoa 00. Oi «nu iu. wnn no 
change to the Group Pointer. 

WhenG4, G2.G1 = 111 and E2. El •> 11, no incrementing takes 
place and only the Status register will be available through the 
dala port. Nole that the Status register can also always be read 
directly through the Control port. 

For all ol these auto-sequence modes, it an 8-bit data bus is used, 
the Byte pointer will toggle after every data transfer to allow Ihe 
least and most significant bytes lo be transferred belore the 
Element or Group Relds are incremented. 

Prefetch Circuit 

In order lo minimize the read access time to internal Am9513 
registers, a prefetch circuit is used for all read operations through 
the Data Port. Following each read or write operation through the 
Data Port, the Data Pointer register is updated to point to the next 
register to be accessed. Immediately following this update, the 
new register data is transferred to a special preletch latch at the 
interface pad logic. When the user performs a subsequent read of 
the Dala Port, the data bus drivers are enabled, outputting the 
pretelched dala on the bus. Since the internal data register is 
accessed prior to the start of the read operation, its access time is 
transparent to Ihe user. In order to keep Ihe prefetched data 
consistent with the data pointer, prefetches are also performed 
after each write to the Data Port and alter execution at the "Load 
Data Pointer" command. The following rules should be kept in 
mind regarding Data Port Transfers. 

1 . The Data Pointer register should always be reloaded before 
reading Irom the Data Port if a command other than "Load 
Data Pointer" was issued lo Ihe Am9513 following the last 
Data Port read or write. The Data Pointer does not have lo be 
loaded again it the first Data Port transaction after a command 
entry is a write, since the Data Port write will automatically 
cause a new prefetch lo occur. 

2. Operating modes N. O, Q and R allow the user to save the 
counler contents in the Hold register by applying an active- 
going gate edge. If the Data Pointer register had been pointing 
to the Hold register in question, the preletched value will not 
correspond to the new value saved in the Hold register. To 



avoid reading an incorrect value, a new "Load Data Pointer" 
commano snouto oe issued belore attempting lo read the 
saved data. A Data Port write (to another register) will also 
initiate a prefetch; subsequent reads will access the recently 
saved Hold register data. Many systems will use the "saving" 
gale edge to interrupt the host CPU. In systems such as this 
Ihe interrupt service routine should issue a "Load Data 
Pointer" command prior to reading the saved data. 

Status Register 

The 8-bit read-only Status register indicates the stale of the Byte 
Pointer bit in the Dala Pointer register and the slate of the OUT 
signal lor each of the general counters. See Figures 11 and 19. 
The OUT signals reported are those internal to the chip after the 
polarity-select logic and just before Ihe 3-slale interface buffer 
circuitry. 

The Status register OUT bit reflects an active-high or active-low 
TC output, or a TC Toggled output, as programmed in the Output 
Control Field of the Counler Mode register. Thai is, it reflects the 





Element Cycle 


Hold Cycle 




Mode 


Load 


Hold 


Hold 




Register 


Regleter 


Register 


Register 


Counter 1 


FF01 


FF09 


FF11 


FFI9 


Counter 2 


FF02 


FF0A 


FF,2 


FF1A 


Counler 3 


FF03 


FF0B 


FF13 


FF1B 


Counler 4 


FF04 


FFOC 


FF14 


FF1C 


Counter 5 


FF05 


FF00 


FF15 


FF1D 



Master Mode Register - FF17 
Alarm 1 Register > FF07 
Alarm 2 Register = FF0F 



Notes: 

1 . All codes are in hex. 

2. When used with an 8-bit bus, only the two low order hex digits 
should be written lo the command port; the 'FF' prefix should be 
used only for a 16-bil data bus interlace. 

Figure 9. Load Data Pointer Commands. 



Am9513 



> 



exac! state ot the CUT pin. When the Low Impedance to Ground 
Output option (CM2-CM0 • 003) is selected, the Status register 
will retted an active-high TC Output. \ 
Output option (CM2-CM0 = 100) is s 
will reflect an active-tow TC output. 

For Counters 1 and 2, the OUT pin will relied the comparator 
output il the comparators are enabled. The Status register bit and 
OUT pin are adive high it CM2 = and adive-low if CM2 ■= 1. 



When the High Impedance option is selected and the comparator 
Is enabled, the status register bit will refled an active-high com- 
parator output. When the Low Impedance to Ground option is 
seleded and the comparator is enabled, the status register bit will 
refled an adive-low comparator output. 

The Status register is normally accessed by reading the control 
port (see Figure 7) but may also be read via the data port as part 
of the Control Group. 







Counter 1 Hold Reg. 
} 

Counter 2 Hold Reg. 
I 



Counter 5 Hold Reg. 



HOLD CYCLE 



Alarm Reg. 1 
I 

Alarm Reg. 2 

I 

Master Mode Reg. 



Counter 1 Mode Reg. 

I 

Counter 1 Load Reg. 

I 

Counter 1 Hold Reg. 

I 

Counter 2 Mode Reg. 
I 

Counter 2 Load Reg. 
I 

Counter 2 Hold Reg 
\ 

1 



Counter 5 Hold Reg. 



ELEMENT CYCLE 



Status Reg. 



CONTROL GROUP CYCLE STATUS CYCLE 



Figure 10. Data Pointer Sequencing. 



DATA PORT REGISTERS 
Counter Logic Groups 

As shown in Figures 3 and 4, each ol the five Counter Logic 
Groups consists of a 16-bit general counler with associated 
control and output logic, a 16-bit Load register, a 16-bit Hold • 
register and a 16-bit Mode register. In addition, Counter Groups 1 
and 2 also include 16-bit Comparators and 16-bit Alarm registers. 
The comparator/alarm functions are controlled by the Master 
Mode register^ The operation ot the Counter Mode registers is 
the same (or all five counters. The host CPU has both read and 
write access lo ail registers in the Counter Logic Groups through 
the data port. The counter itself is never directly accessed. 

The 1 6-bit read/write Load register is used to control the effective 
period of the general counter. Any 16-bit value may be written 
into the Load register. That value can then be transferred into the 
counter each time that Terminal Count (TC) occurs. "Terminal 
Count" is defined as that period of time when the counter con- 
tents would have been zero if an external value had not been 
transferred into the counter. Thus the terminal count frequency 
can be the input frequency divided by the value in the Load 
register. In all operating modes the contents of either Load or 
Hold register will be transferred into the counter when TC occurs. 
In cases where values are being accumulated in the counter, the 
Load register action can be transparent by filling the Load regis- 
ter with all zeros. 

The 16-bit read/write Hold register is dual-purpose. It can be 
used in the same way as the Load register, thus offering an 
alternate source for modulo definition for the counter. The Hold 
register may also be used to store accumulated counter values 
for later transfer to the host processor. This allows the count to be 
sampled while the counting process proceeds. Transfer of the 
counter contents into the Hold register is accomplished by the 
hardware interlace in some operating modes or by the software 
SAVE command at any time. 

Counter Mode Register 

The 16-bit read/write Counter Mode register controls the gating, 
counting, output and source select functions within each Counter 
Logic Group. The "Counter Mode Control Options" section of this 
data sheet describes the detailed control options available. 
Figure 18 shows the b>i assignments for the Counter Mode 
registers. 

Alarm Registers and Comparators 

Added functions are available in the Counter Logic Groups for 
Counters 1 and 2 (see Figure 3). Each contains a 16-bit Alarm 
register and a 16-bit Comparator. When the value in the counter 
reaches the value in the Alarm register, the Comparator output 
will go true. The Master Mode register contains control bits to 
individually enable/disable the comparators. When enabled, the 



SR7 


SR6 


SR5 


SR4 


SR3 


SR2 


SR1 


SRO 



1 1 OUT 4 OUT 2 BYTE 

POINTER 
OUT 5 OUT 3 OUT 1 

MOS-17S 

Figure M. Status Register Bit Assignments. 



Am9513 



comparator output appears on the OUT pin of the associated 
counter in place ol the normal counter output. The output will 
remain true as long as the comparison is true, that is, until the next 
input causes the count to change. The polarity ol the Comparator 
output will be active-high if the Output Control field of Ihe Counter 
Mode register is 001 or 010 and active-low if the Output Control 
field is 101. 

REGtSTER ACCESS" ' 
Information Transfer Protocols 

The control signal configurations for all information transfers on 
the Am9513 data bus are summarized in Figure 12. The interface 
conlrol logic assumes these conventions: 

1 . RD a_nd_WR are_ never adive at the same time. 

2. RD, WR and C/D are ignored unless CS is Low. 
Command Initiation 

The procedure for executing a command is as follows: 

1 . Establish the appropriate command on the DB0-DB7 lines. 
Figure 21 lists the command codes. When using the Am9513 
in 16-bit mode, data bus lines DB8-OB15 should be set high 
during the write operation. In 8-bit data bus mode, DB13-DB1 5 
should be set high during the write operation. 

2. Establish a High on the C/p input. 

3. Establish a Low on the CS input. 

4. Establish a Low on the WR input. 

0. Sometime aner the minimum WR low pulse duration has been 
achieved, drive WR high, taking care the CS, C/D and data 
setup times are met (see Timing Diagram). 

6. After meeting the required CS. C/D and data hold times, these 

signals can be changed (see Timing Diagram). 
A new read or write operation to the Am95l3 should not be 
perlormed until the write recovery time is met (see Timing 
Diagram). 

Setting the Data Pointer Register 

The Data Pointer register seleds which register is to be accessed 
through the data port. The Pointer is set as follows: 

1. Using Figures 8 and 9, select the appropriate Data Pointer 
Group and Element codes for the register lo he accessed. 
Note that two codes are provided for the Hold registers, to 
accommodate both the Hold Cycle and Element Cycle auto- 
sequencing modes shown in Figure 10. If auto-sequencing is 
disabled, either Hold code may be used. 



Signal 
Configuration 


Data But 


CS 


C/D 


RD 


WR 


Operation 













Transler contents of register addressed 
by Data Pointer to the data bus. 








1 





Transfer contents of data bus to data 
register addressed by Data Pointer. 





1 





1 


Transler contents of Status register to 
data bus. 





1 


t 





Transfer contents of data bus into 
Command register. 


X 


X 


1 


1 


No transfer. 


1 


X 


X 


X 


No transfer. 


X 


X 








Illegal Condition. 



Figure 12. Data Bus Transfers. 



2 Using the "Wilting lo Ihe Command Register- procedure 
given above, write the appropriate "Load Data Pointer" com- 
mand to the Command register. Note that the command 
summary in Figure 21 has the Group field and Element field 
switched Irom the format given in Figure 6. 
The Data Pointer register is now set. Selling the Data Pointer 
register automatically sets the Byte Pointer to t, indicating a least 
significant oyte is expeded for 6-bit data bus interfacing. If Master 
Mode register bit MM14 = 0, the Data Pointer will automatically 
sequence through one of the cycles shown in Figure 10 after 
reading or writing each register. For convenience, bit MM14 can 
be set or cleared by software command. 

Reading the Status Register 

The procedure for reading the Status register through the Control 
port is given in the following. The Status register can also be read 
from the data port as outlined in the Reading from the Data Port 
section of this data sheet. 

1 . Establish a High on the C/D input 

2. Establish a Low on the CS input. 

3. Alter the appropriate CS and C/D setup time (see Timing 
Diagram) make RD Low. 

4. Sometime after RD goes Low, the Status register contents will 
appear on the data bus. These lines will contain the informa- 
tion asjong as RD is Low. If the state of an OUT pin changes 
while RD is Low, this will be refleded by a change in the 

5. RD can be driven Highto conclude the read operation after 
meeting the_minimum RD pulse duration. 

6. CS and C/D can change after meeting the appropriate hold 
time requirements (see Timing Diagram). 

A new read or write operation to the Am95!3 should not be 
attempted until the read recovery time is met (see Timing 
Diagram). 

Writing to the Data Port 

The registers which can be written to through the data port are the 
Load, Hold and Counter Mode registers for Counters 1 through 5. 
the Alarm registers for Counters 1 and 2 and the Master Mode 
register. The procedure for writing to these three registers is as 
follows: 

1 . Prior to performing the actual write operation, the Data Pointer 
should be set lo point lo the register lo be written lo, as outlined 
above in the "Setting the Data Pointer" sedion of this data 
sheet. In cases where auto-sequencing of the Data Pointer is 
used, the Pointer has to be set only once to the first register in 
the sequence. When auto-sequencing is disabled, repetitive 
accesses can be made lo the same register wilhout reloading 
the Data Pointer each time. 

2. Establish the appropriate data on the DB0-DB7 lines (8-bit bus 
mode) or DB0-DB15 (16-bit bus mode). When using the 8-bit 
bus mode, data bus lines DB13-OS15 should be set High 
during the write operation and DB0-DB7 should be set to the 
tower data byte for the first write and to the upper data byte for 
the second write. 

3. Establish a Low on the C/E) input. 

4. Establish a Low on the CS input. 

5. Establish^ Low on the WR input. 

6. Drive WR High sometime after the minimum WR low pulse 
duration has been achieved, taking care the CS, C/D and data 
setup limes are met (see Timing Diagram). 

7. After meeting the required CS. C/D and data hold times, these 
signals can be changed (see Timing Diagram). 

8. After meeting the write recovery time (see Timing Diagram) a 
new read or write operation can be performed. For the 8-bit 
bus mode, steps 2 through 7 should be repeated, this time 



Am9513 



> 

I 



placing the high data byte_on pins DB0-DB7. The user is net 
required to drive CS or C/0 High between successive reads or 
writes, although this is 
Reading From the DaU 
The registers which can be read from trie Data port are the Load, 
Hold and Counter Mode registers for Counters 1 through 5, the 
Alarm registers for Counters 1 and 2, the Master Mode register 
and the Status register. The Status register can also be read from 
the Control p 



port. The procedure lor reading these registers is as 
follows: > ' 

1 . Prior to performing the actual read operation, the Data Pointer 
should be set to point to the register to be read, as outlined in 
the "Settling the Data Pointer" section of this data sheet. In 
cases where auto-sequencing of the Data Pointer is used, the 
Pointer has to be set only once to the first register in the 
sequence. When auto-sequencing is disabled, repetitive ac- 
cesses can be made to the same register without reloading the 
Data Pointer each time. Special care must be taken to reset 
the Data Pointer after issuing a command other than "Load 
Data Pointer" to the Am9513 or when operating a counter in 
modes N, 0. Q or R. See the "Prefetch Circuit" section of this 
document lor elaboration. 
I. Establish a Low on the C/D input. 

3. Establish a Low on the CS input. 

4. Establish a Low on RD after waiting for the appropriate CS and 
C/D setup time (see Timing Diagram). 

5. Sometime after RD goes Low, the register contents will ap- 

register byte will appear on DB0-DB7. In addition, in 1 6-bit bus 
mode, the upper register byte will appear on DB8-DB15. For 
8-bit bus mode, pins DB8-DB15 are not driven by the Am9513 



This information will remain stable as long as RD is Low. II the 
register value is changed during the read, Ihe change will not 
be rellected by a change in the data being read, for the 
reasons outlined In the "Prefetch Circuit" section ol this 
document. 

6. RD can be driven Highjo conclude the read operation after 
meeting the minimum RD pulse duration. 

7. CS and C/D can change after meeting appropriate hold time., 
requirements (see Timing Diagram). - - 

8. After waiting the minimum read recovery time (see Timing 
Diagram), a new read or write operation can be started. For 
8-bit bus mode, steps 2 through 7 should be repeated to read 
out Ihe high register byte on DB0-DB7. (tf the Status register Is 
being read in 8-bit mode, the two reads will return the Status 
register each time. Ir> 16-bit mode, reads from the Status 
register return undefined data on DB8-DB15.) The user is not 
required to drive CS or C/D High between successive reads or 
writes, although this is permissible. 

MASTER MODE CONTROL OPTIONS 

The 16-bit Master Mode (MM) register is used to control those 
internal activities that are not controlled by the individual Counter 
Mode registers. This includes frequency control, time-of-day op- 
eration, comparator controls, data bus width and data pointer 
sequencing. Figure 13 shows the bit assignments tor the Master 
Mode register. This section describes the use of each control 
lield. 

II» M« . — «»■'■■ Kit* UMUL l«i13 «>w4 MktlA ™ K*> InHi. 

vidually set and reset using commands issued to the Command 
register. In addition they can all be changed by writing directly to 




0000 . 

0001 ■ 

0010 ■ 

0011 ■ 

0100 ■ 

0101 ■ 

0110 ■ 

0111 . 

1000 ' 

1001 • 

1010 ■ 

1011 ■ 

1100 ■ 

1101 ■ 

1110 ■ 

1111 . 



F1 

SRC 1 
SRC 2 
SRC 3 
SRC 4 
SRC 5 
GATE 1 
GATE 2 
GATE 3 
GATE 4 
GATE 5 
Fl 
F2 
F3 
F4 
FS 



MM 15 


MM14 


MM 13 


MM12 


MM11 


MM 10 


MM9 


WMfi 


MM7 


MM6 


MMS 


MM4 


MM3 


MM2 


MM1 


MM0 



L 



FOUT Gate 

- FOUT On 

1 . FOUT Oft (Low Z to GND) 
Data Sua Width 

■= B-Bit Bus 

1 m 16- Bit Bus 
Data Pointer Control 

= Enable Increment 

1 - Disable Increment 
Scalar Control 

= Binary Division 

1 - BCD Division 



Compare 2 Enable — ' 

- Disabled 

1 - Enabled 
Compare 1 Enable 

- Disabled 

1 - Enabled 

Tlme-of-Day Mode 

00 - TOD Disabled 

01 '- TOD Enabled; -t- 5 Input 

10 • TOD Enabled; ♦ 6 Input 

11 - TOD Enabled: * 10 Input 



Figure 13. Master Mod« Register Bit Assignments. 



7-118 



Am9S13 



Figure 14. Tlm*-of-Day Storage Configuration. 



After power-on reset or a Master Reset command, the Master 
Mode register is cleared to an all zero condition. This results in the 
following configuration: 

Time-of-day disabled 

Both Comparators disabled 

FOUT Source is Irequency F1 

FOUT Divider set lor divide-by-16 

FOUT galed on 

Data Bus 8 bits wide 

Data Pointer Sequencing enabled 

Frenuonrv <VaLsr mJOmm in K;~-,~, 



Time-of-Day 

Bits MM0 and MMl ot the Master Mode register specify the 
time-of-day (TOD) options. When MM0 - and MM1 . 0. the 
special logic used lo implement TOD is disabled and Counters 1 
and 2 will operate in exactly the same way as Counters 3, 4 and 5 
When MMO = 1 or MM1 = 1, additional counter decoding and 
control logic is enabled on Counters 1 and 2 which causes their 
decades to turn over at the counts that generate appropriate 
24-hour TOD accumulations. 

Figure 14 shows the counter configurations for TOD operation 
The. two most significant decades ol Counter 2 contain the 
"hours" digits and they can hold a maximum count of 23 hours. 
The two least significant decadesolCounter2 indicate "minutes" 
and will hold values up to 59. The three most significant decades 
of Counter l indicate "seconds" and will contain values up to 
59.9. The leasl significant decade of Counter 1 is used to scale 
the input frequency in order to output tenth-of-second periods into 
the next decade. It can be set up lo divide-by-five (MMO = 1 , MM1 
* 0), divide-by-six (MMO * 0. MM1 a 1), or divide-by-ten (MMO = 
1, MM1 - i). The input frequency, therefore, for real-time clock- 




•"*"- iSSSS 



LCVtL 
CATC 

COMJnOL 



Figure 15. Gating Control. 



ir.g can be, respectively, 50Hz. 60Hz or 100Hz. With divide by-ter, 
specilied and with 100Hz input, the least significant decade ol 
Counter 1 accumulates time 'm hundredths ot seconds (tens of 
milliseconds). For accelerated lime applications other input fre- 
quencies may be useful. .. '.: ..-. : l 
The input lor Counter 2 should be the TC output ol Counter.), 
connected either internally or externally, lor TOD operation. Both 
counters should be set up lor BCD counting. The Load registers 
should be used to initialize the counters to Ihe proper time. Either 
count up or count down may be used. ■ ■ ■ 
To read the lime, a SAVE command should be issued to Counters 
1 and 2. Because counts ripple between the counters, the possi- 
bility exists ol the SAVE command occurring after Counter 1 has 
counted but before Counter 2 has. This would result in an incor- 
rectly saved time. To guard against this. Counter 2 should be 
resaved il Counter 1 's saved value indicates a ripple carry/borrow 
may have been generated. In other words. Counter 2 should be 
resaved If the value saved from Counter t is (up counting) 
59.94 (down counting. MM1-MM0 - 01), 59.95 (down counting' 
MM1-MM0- 1 0), or 59.99 (down counting, MM1 -MMO - 11). By 
the time this lest is performed and Counter 2 Is resaved, any 
rippling cany/borrow will have updated Counter 2. 

Comparator Enable 

Bits MM2 and MM3 control the Comparators associated with 
Counter 1 and 2. When a Comparator is enabled its out™ it is 
substituted lor the normal counter output on the associated OUTl 
or OUT2 pin. The comparator output will be active-high if the 
output control.field ol the Counter Mode register is 001 or 010 and 
active low lor a code of 101 . Once the compare output is true. It will 
remain so until the count changes and the comparison therefore 
goes false. 

The Iwo Comparators can always be used Individually in any 
operating mode. One special case occurs when Ihe time-of-day 
option is invoked and both Comparators are enabled. The opera- 
lion ol Comparator 2 will then be conditioned by Comparator 1 so 
that a lull 32 -bit compare must be true in order to generate a true 
signal on OUT2. OUT 1 will continue, as usual, to reflect Ihe slate 
of ihe 16-bit comparison between Alarm 1 and Counter I. 
FOUT Source 

Master Mode bits MM4 through MM7 specify the source input lor 
the FOUT divider. Fifteen inputs are available for selection and 
they include the five Source pins, the five Gate pins and the five 
internal frequencies derived from the oscillator. The 16th combi- 
nation of Ihe four control bits (all zeros) is used lo assure that an 
active frequency is available at the input to the FOUT divider 



8ils MM8 throught MM11 specify the dividing ratio for the FOUT 
Divider. The FOUT source (selected by bits MM4 through MM7) is 
divided by an integer value between l and 16. inclusive, and is 
then passed to the FOUT output buffer. After power-on or resel. 
the FOUT divider is set to divide-by-16. 

FOUT Gate 

Master Mode bit MM12 provides a software gating capability lor 
the FOUT signal. When MM12 » 1, FOUT is off and in a low 
impedance state to ground. MM12 may be set or cleared in, 
conjunction with the loading of the other bits in the Master Mode 
register; alternatively, there are commands that allow MMl 2 lo be 
individually set or cleared directly without changing any other 
Master Mode bits. After power-up or resel. FOUT is gated on. 



7-119 



When changing the FOUT divider ratio or FOUT source. transient 
pulses as short as hall Ihe period ol !ha FOUT source may appear 
on the FOUT pin. Turning ihe FOUT gale on or otl can also 
generale a transient. This should be considered when using 
FOUT as a system clock source. 

But Width 

Bf|'MM13 controls the multiplexer at the data bus interface In 
orcler to configure the part for an 8-bit or 16-bit external bus. The 
internal bus is always 16 bits wide. When MM13 = 1 , 16-bit data is 
transferred directly between the internal bus and an 16 ol Ihe 
external bus lines. In this configuration, the Byle Pointer bit in the 
Data Pointer register remains set at all times. When MM13 - 0. 
16-bit Internal data Is transferred a byte at a time to and Irom the 
eight low-order external data bus lines. The Byte Pointer bit 
toggles with each byle transler in this mode. 
When the Am9513 Is set to operate with an 6-bit data bus width, 
pins DB8 through DB15 are not used tor the data bus and are 
available tor other functions. Pins DB13 through DB15 should be 
tied high. Pins DB8 through DB12 are used as auxiliary gating 
Inputs, and are labeled GATE1A through GATE5A respectively. 
The auxiliary gate pin, GATENA, Is logically ANDed with the gate 
input to Counter N, as shown in Figure 1 5. The output ot Ihe AND 
gate is then used as the gating signal tor Counter N. 

Data Pointer Sequencing 

Bit MM14 controls the Data Pointer logic to enable or disable Ihe 
automatic i«qu<n u v " m »• " 1 '<" ' ■* ~ '.*•»«•" *" "* 
ol the Data Pointer can be changed only directly by entering a 
command. When MM14 = 0, several types ol automatic 
sequencing ot the Data Pointer are available. These are de- 
scribed in the Data Pointer register section ol this document. 
Thus the host processor, by controlling MM14, may repetitively 
read/write a single internal location, or may sequentially read/ 
write groupsof locations. Bit MM14 can be loaded by writing to the 
Master Mode register or can be set or cleared by software 
command. 
Scaler Ratloe 

Master Mode bit MMI5 controls Ihe counting configuration ol ihe 
Frequency Scaler counter. When MM15 = 0. the Scaler divides 



•he oscillator frequency In binary steps so that each sub- 
Irequency is 1/16 ol the preceding Irequency. When MM15 = 1, 
the Scaler divides in BCD steps so thai adjacent Irequencies are 
related by ratios ol 10 instead ot 16 (see Figure 16). 

OPERATING MODE DESCRIPTIONS 
Counter Mode register bits CM15-CM13 andCM7-CM5 select the 
operating mode (or each counter (see Figure' 17). To simplify 
references to a particular mode, each mode is assigned a letter 

from A through X. - • • ■■■■ *• 

To keep the following mode descriptions concise and to the point, 
the phrase "source edges" is used to refer to active-going source 
edges only, not to Inactive-going edges. Smilarly, the phrase 
"gate edges" refers only to active-going gate edges. Also, again 
to avoid verbosity and euphuism, the descriptions of some modes 
stales that a counter Is stopped or disarmed "on a TC. Inhibiting 
further counting." As is fully explained In the TC section of this 
data sheet, for these modes the counter Is actually stopped or 
disarmed following the active-going source edge which drives the 
counter out ol TC. In other words, since a counter In the TC state 
always counts, irrespective of its gating or arming status, the 
stopping ot disarming of the count sequence Is delayed until TC 
is terminated. 

MODE A 

Software-Triggered Strobe with No Hardware Gating 

Mode A is one ol Ihe simplest operating modes. The counter will 
be available lor counting source edges when it is Issued an ARM 
command. On each TC the counter will reload Irom the Load 
register and automatically disarm itself, inhibiting lurther count- 
ing. Counting will resume when a new ARM command is issued. 

MODE B 

Software-Triggered Strobe with Level Gating 

Mode B is identical to Mode A except that source edges are 
counted only when the assigned Gale is active. The counter must 
be armed before counting can occur. Once armed, the counter 
will count all source edges which occur while the Gate is active 
and disregard those edges which occur while the Gate is inactive. 













- 


osc 






-r=v 


— 4 BITS ' 


4 WTS 


4 WT5 





FREQUENCY SCALER 



BCD Binary 
Scaling Scaling 
Frequency MM15 = 1 MM15 = 



F1 




OSC 




OSC 


F2 


F1 


♦ 10 


F1 


* 16 


F3 


F1 


* 100 


F1 


+ 256 


F4 


F1 


* 1,000 


F1 


* 4.096 


F5 


F1 


+ 10,000 


F1 


* 65.536 



Figure 16. Frequency Scaler Ratios. 




Am9513 



Opti 8 ling Mode 


A 


B 


c 


D 


E 


F 


G 


H 


1 


J 


K 


L 


Special Gale (CM 7) ., 






































Reload Source (CM6) 






















1 




t 




1 


Repetition (CMS) 











1 


1 


1 













1 




Gate Control (CM 1$ -CM 13) 


000 


LEVEL 


EDGE 


000 


LEVEL 


EDGE 


000 


LEVEL 


EDGE 


000 


LEVEL 


EDGE 


Count to TC once, then disarm 


X 


X 






















Count to TC twtce. then disarm 














X 


X 


X 








Count lo TC repeatedly 


























Gate input does not gate counter input 


X 






X 






X 






X 






Count only during active gale level 




X 






X 






X 






X 




Start count on active gale edge and 
slop count on next TC. 






X 






X 














Start count on active gale edge and 

stop count on second TC. 


















X 






X 


No hardware retrSggering 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


Reload counter from Load Register 

on TC 


X 


X 


X 


X 


X 


X 














Reload counter on each TC. a«em*iir>g 
reload source between Load and Mold 
Registers. 














X 


X 


X 


X 


X 


X 


Transtef Load Register into counter on 
each TC irial gale is LOW; wansle< Mold 
Register into counter on each TC thai 




















































On active gate edge transfer counter 
into Hold Reg.ster and then reload 
counter Irom Load Regisier 



























Operating Mode 


M 




o- 


•» 





R 


s 


T 


U 


V 


w 


X 


Special Gate (CM7) 


1 


1 


1 


1 


t 


1 




1 


1 


! 






Reload Source (CM6) 




















1 


\ 


1 






1 


Ftepewon (CMS) 











1 




1 











1 






Gale Control (CMI5-CM13) 


000 


LEVEL 


EDGE 


000 


LEVEL 


EDGE 


000 


LEVEL 


EDGE 


000 


LEVEL 


EDGE 


Count lo TC once, then disarm 




X 


X 




















Count to TC twice, then aisarrrt 














X 












Count to TC repeatedly 










X 


X 








X 






Gale input does no I gate counter mpui 














X 






X 






Count only rjunng aciive gate level 




X 






X 
















Start count on active gate edge and 
stop count on next TC. 






X 




















Stan count on aciive gale edge and 
stop count on second TC. 


























No hardware retnggering 














X 






X 






Reload counter from Load Regisier 

on TC 




X 


X 




X 


X 














Reload counter on each TC. alternating 
reload source between Load and Mc*3 
Registers 


























Transler Load Regisier *no counter on 
each TC that gate is LOW; transler HoM 
Rec-ster mio counter on aach TC that 
gate is HIGH. 














X 






X 






On active gale edge transfer counter 
mio Hold Register and Ihen reload 
counter Irom LO*d Register. 




X 


X 




X 


X 

















Note: Operating modes M. P. T. U. W and X ar« r«s«rv«d and should not M used 



Figure 17. Counter Control Interaction. 



Am9513 



This permits the Gale to turn the count process on and off. On 
each TC the counter will reload from the Load register and au- 
tomatically disarm itself, inhibiting further counting until a new 
ARM command is issued. 

MODE C 

Hardware-Triggered Strobe 

Mode C Is identical to Mode A. except that counting will not begin 
until a Gate edge is applied to the armed counter. The counter 
must be armed before application of the triggering Gate edge; 
Gate edges applied to a disarmed counter are disregarded. The 
counter will start counting on the first source edge after the 
triggering Gate edge and will continue counting until TC. At TC, 
the counter will reload from the Load register and automatically 
disarm hseff. Counting will then remain inhibited until a new ARM 
command and a new Gate edge are applied in that order. Note 
that after application of a triggering Gate edge, the Gate input will 
be disregarded for the remainder of the count cycle. This differs 
from Mode B. where the Gate can be modulated throughout the 
count cycle to stop and start the counter. 

MODE D 

Rate Generator wtth No Hardware Gating 

Mode D is typically used in frequency generation applications. In 
this mode, the Gate input does not affect counter operation. Once 
armed, the counter will count to TC repetitively. On each TC the 
counter will reload itself from the Load register; hence the Load 

rente! or v/all ia riuluiminnr lha tirna Kntu/Mn TPp A fm ,irf i l Mii t 

rate generator may be obtained by specifying the TC Toggled 
output mode in the Counter Mode register. 

MODE E 

Rate Generator with Level Gating 

Mode E is identical to Mode D. except the counter will only count 
those source edges which occur while the Gate input is active. 
This feature allows the counting process to be enabled and 
disabled under hardware control. A square wave rate generator 
may be obtained by specifying the TC Toggled output mode. 

MODE F 

Non-Retrlggerable One-Shot 

Mode F provides a non -re trigger able one-shot timing function. 
The counter must be armed before it will function. Application of a 
Gate edge to the armed counter will enable counting. When the 
counter reaches TC, it will reload itself from the Load register. The 
counter will then stop counting, awaiting a new Gate edge. Note 
that unlike Mode C. a new ARM command is not needed after TC, 
only a new Gate edge. After application of a triggering Gate edge, 
the Gate input is disregarded until TC. 

MODE G 

Software-Triggered Delayed Pulse One-Shot 

In Mode G, the Gate does not affect the counter's operation. Once 
armed, the counter will count to TC twice and then automatically 
disarm itself. For most applications, the counter will initially be 
loaded from the Load register either by a LOAO command or by 
the last TC of an earlier timing cycle. Upon counting to the first TC, 
the counter will reload itself from the Hold register. Counting will 
proceed until the second TC, when the counter will reload itself 
trom the Load register and automatically disarm itself, inhibiting 
further counting. Counting can be resumed by issuing a new ARM 
command. A software -triggered delayed pulse one-shot may be 
generated by specifying the TC Toggled output mode in the 
Counter Mode register. The initial counter contents control the 
delay from the ARM command until the output pulse starts. The 
Hold register contents control the pulse duration. 



MODE H 

Software-Triggered Delayed Pulse One- Shot with Hardware 
Gating 

Mode H is idenlical lo Mode G except that the Gale input is used 
to qualify which source edges are lo be counted. The counter 
must be armed for counting to occur. Once armed, the counter will 
count all source edges that occur while the Gate is active and 
disreaard those source edges that occur while the Gate is inac- 
tive. This permits the Gate to turn the count process on and off. As 
with Mode G. the counter will oe reloaded from the Hold register 
on the first TC and reloaded from the Load register and disarmed 
on the second TC. This mode allows the Gate to control the 
extension of both the initial output delay time and the pulse width. 

MODE I 

Hardware-Triggered Delayed Pulse Strobe 
Mode I is identical to Mode G, except that counting will not begin 
unlil a Gate edge is applied to an armed counter. The counter 
must be armed before application of the triggering Gate edge; 
Gate edges applied to a disarmed counter are disregarded. An 
armed counter wilt slart counting on the first source edge after the 
triggering Gate edge. Counting will then proceed in the same 
manner as in Mode G. After the second TC, the counter will 
disarm itself. An ARM command and Gate edge must be issued in 
this order lo restart counting. Nole that after application of a 
triggering Gale edge, the Gate input will be disregarded until the 
second TC. This differs from Mode H. where the Gate can be 



counter. 
MODE J 

Variable Duty Cycle Rate Generator with No Hardware 
Gating 

Mode J will find the greatest usage in frequency generation 
applications with variable duty cycle requirements. Once armed, 
[he counter will count continuously until it is issued a DISARM 
command. On the first TC. the counter will be reloaded from the 
Hold register. Counting will then proceed unlil the second TC at 
which time the counter will be reloaded from the Load register. 
Counting will continue, with the reload source alternating on each 
TC, until a DISARM command is issued lo the counter. (The third 
TC reloads from the Hold agister, the fourth TC reloads from the 
Load register, etc.) A variwle duty cycle output can be generated 
by specifying the TC Toggled output in the Counter Mode regis- 
ter. The Load and Hold values then directly control the output duty 
cycle, with high resolution available when relatively high count 
values are used. 

MODE K 

Variable Duty Cycle Rate Generator with Level Gating 

Mode K is idenlical to Mode J except thai source edges are only 
counted when the Gate is active. The counter musl be armed for 
counting to occur. Once armed, the counter will count all source 
edges which occur while the Gale is active and disregard those 
source edges which occur while the Gate is inactive. This permits 
the Gate to turn the count process on and off. As with Mode J. the 
reload source used will alternate" on each TC. starting with the 
Hold register on Ihe first TC after any ARM command. When the 
TC Toggled output is used, this mode allows the Gale to modulale 
the duty cycle of the output wavelorm. It can affect both ihe high 
and low portions of the output waveform. 

MODE L 

Hardware-Triggered Delayed Pulse One-Shot 

Mode L is similar to Mode J except that counting will not begin 
until a Gate edge is applied to an armed counter. The counter 
must be armed before application of the triggering Gate edge; 



Am9513 



Gate edges applied to a disarmuc counier are disregaroeo. The 
counier will start counting source edges after the triggering Gate 
edge and counting will proceed until the second TC. Nole that 
after application of a triggering Gate edge, the Gale input will be 
disregarded for ihe remainder of the count cycle. This differs trom 
Mode K, where the gate can be modulaled Ihroughout the count 
cyde to stop and start the counter. On the first TC after application 
of the triggering Gate edge, the counter will be reloaded from the 
Hold register.' On the second TC, the counier will be reloaded 
from the Load register and counting will stop until a new gate edge 
Is issued to the counter. Note that unlike Mode K. new Gate edges 
are required after every second TC to continue counting. 

MODE N 

Software-Triggered Strobe with Level Gating and Hardware 
Retriggering 

Mode N provides a softwam-triggered strobe with level gating 
that is also hardware retriggerable. The counter must first be 
issued an ARM command before counting can occur. Once 
armed, the counter will count all source edges which occur while 
the gate is active and disregard those source edges which occur 
while the Gate is inactive. This permits the Gate to turn the count 
process on and off. After the issuance of an ARM command and 
the application of an active Gale, the counter will count lo TC. 
Upon reaching TC, the counter will reload from the Load register 
and automatically disarm itself, inhibiting further counting. 
Counting will resume upon the issuance ol a new ARM command 

All arliufl.nnlnfi (zZ*.. Z^i^ZZ '.ZZ'JZt '.Z CTTrCd mSSmmi nm 

cause a retrigger operation. Upon application of the Gate edge, 
the counter contents will be saved in the Hold register. On the first 
qualified source edge after application of Ihe retriggering gale 
edge the contents of the Load register will be transferred inio the 
counter. Counting will resume on the second qualified source 
edge after the retriggering Gate edge. Qualified source edges are 
active-going edges which occur while the Gate is active. 

MOOE O 

Software-Triggered Strobe with Edge Gating and Hardware 
Retriggering 

Mode O is similar to Mode N. except that counting will not begin 
until an active-going Gate edge is applied to an armed counter 
and the Gate level is not used to modulate counting. The counter 
must be armed before application of the triggering Gate edge; 
Gate edges applied to a disarmed counter are disregarded. Irres- 
pective of the Gate level, the counter wifl count ail source edges 
after the triggering Gate edge until Ihe first TC. On the first TC the 
counier will be reloaded from the Load register and disarmed. A 
new ARM command and a new Gate edge must be applied in that 
order to initiate a new counting cycle. Unlike Modes C. F, I and L, 
which disregard the Gate input once counting starts, in Mode O 
Ihe count process will be retriggered on all active-going Gate 
edges, including the first Gate edge used to start the counter. On 
each retriggering Gate edge, the counter contents wifl be trans- 
ferred into the Hold register. On the first source edge after the 
retriggering Gate edge the Load register contents will be transfer- 
red into the counter. Counting wilt resume on the second source 
edge after a retrigger. 

MODE Q 

Rate Generator with Synchronization 
(Event Counter with Auto- ReaoV Reset) 

Mode Q provides a rate generator with synchronization or an 
event counter with auto- re ad/reset. The counter must first be 
issued an ARM command before counting can occur. Once 
armed, the counter will count all source odges which occur while 



me Gale is active and disregard those edges which occur while 
the Gate is inactive. This permits the Gate to turn Ihe count 
process on and off. After the issuance of an ARM command and 
the application of an active Gate, the counter will count to TC 
repetitively. On each TC the counter will reload itself from the 
Load register. The counter may be retriggered at any time by 
presenting an active-going Gale edge to the Gate input. The 
retriggering Gale edge will transfer the contents of the counier 
into the Hold register. The first qualified source edge after the 
retriggering Gate edge will transfer the contents of the Load 
register into the counter. Counting will resume on Ihe second 
qualified source edge after the retriggering gate edge. Qualified 
source edges are active-going edges which occur while the Gate 
is active. ' 

MODE R 

Retriggerable One-Shot 

Mode R is similar to Mode Q, except that edge gating rather than 
level gating is used. In other words, rather than use the Gate level 
lo qualify which source edges to count. Gate edges are used to 
start the counting operation. The counter must be armed before 
application of the triggering Gale edge; Gate edges applied to a 
disarmed counter are disregarded. After application at a Gale 
edge, an armed counter will count all source edges until TC, 
irrespective ol the Gale level. On the first TC the counter will be 
reloaded Irom the Load register and stopped. Subsequent 
^uuuiiiiy will not i*jcur umii a new oaie eage is applied. All Gale 
edges applied to the counter, including the first used lo trigger 
counting, initiate a retrigger operation. Upon application of a Gate 
edge, the counter contents are saved in the Hold register. On the 
first source edge after the retriggering Gate edge, the Load reg- 
ister contents will be iransferred into the counter. Counting will 
resume on the second source edge after the retriggering Gale 
edge. 

MODE S 

In Ihis mode, ihe reload source for LOAD commands (irrespective 
of whether the counter is armed or disarmed) and for TC-initiaied 
reloads is determined by the Gate input. The Gate input in Mode S 
is used only to select the reload source, not to slart or modulate 
counting. When the Gale is Low, the Load register is used; when 
the Gate is High, the Hold regisier is used. Note the Low-Load, 
High-Hold mnemonic convention. Once armed, the counter will 
count to TC twice and then disarm itself. On each TC ihe counter 
will be reloaded from the reload source selected by the Gate. 
Following the second TC. an ARM command is required to stan a 
new counting cycle. 

MODE V 

Frequency-Shift Keying 

Mode V provides frequency -shift keying modulation capability 
Gale operation in this mode is identical to that in Mode S. If the 
Gale is Low, a LOAD command or a TC-induced reload will reload 
ihe counier from the Load regisier. If ihe Gale is High. LOADs and 
reloads will occur from the Hold register. The polarity of the Gale 
only selects the reload source; rt does not start or modulate 
couniing. Once armed, the counter will count repetitively to TC 
On each TC the counier will reload itself from the regisier deter- 
mined by the polarity of the Gale. Counting will continue in ihis 
manner until a DISARM command is issued to the counter. Fre- <i 
quency shift keying may be obtained by specifying a TC Toggled 
output mode in the Counter Mode register. The switching of 
frequencies is achieved by modulating the Gate. 



Am9513 



COUNTER MODE CONTROL OPTIONS 
Each Counter Logic Group includes a 16-bit Counler Mode (CM) 
register used to control all of the indfvidual options available with 
its associated general counter. These options include output 
configuration, count control, count source and gating control. 
Figure 18 shows the bit assignments tor the Counter Mode regis- 
ters. This section describes the control options in detail. Note that 
generally each counter is Independently configured and does not 
depend on information outside its Counler Logic Group. The 
Counter Mode register should be loaded only when the counter is 
Disarmed. Attempts to load the Counter Mode register when the 
counter is armed may result In erratic counter operation." 
After power-on reset or a Master Reset command, the Counter 
Mode registers are initialized to a preset condition. The value 
entered is 0B00 hex and results in the following control 
configuration: 

Output tow impedance to ground 

Count down 

Count binary 

Count once 

Load register selected 

No retriggering 

F1 input source selected 

Positive-true input polarity 

No gating 



Output Control 

Counter mode bits CMO through CM2 specily the output conirol 
configuration. Figure 19 shows a schematic representation of the 
output control logic. The OUT pin may be off and in a high 
impedance state, or H may be off with a low impedance to ground. 
The three remaining valid combinations represent the two bask;* 
output waveforms. 

One output form available is called Terminal Count '(TC) and 
represents the period in time that the counter reaches an equiva- 
lent value of zero. TC will occur on the next count when the 
counter is at 0001 for down counting, at "9999 (BCD) for BCD up 
counting or at FFFF (hex) for binary up counting. Figure 20 shows 
a Terminal Count pulse and an example context that generated it. 
The TC width is determinedly the period of the counting source. 
Regardless of any gating input or whether the counler is Armed or 
Disarmed, the terminal count will go active for only one clock 
cycle. Figure 20 assumes active-high source polarity, counter 
armed, counter decrementing and an external reload value of K. 

The counter will always be loaded from an external location when 
TC occurs; the user can choose Ihe source location and the 
value. If a non-zero value is picked, the counter will never really 
attain a zero stale and TC will indicate the counter state that 
would have been zero had no parallel transfer occurred. 
The other output form, TC Toggled, uses the trailing edge of TC to 
toggle a flip-flop 10 generate an output level instead of a pulse. 



Count Source Selection 



OXXXX = Count on Rising Edge 

1XXXX = Count on Falling Edge 

X0OOO m TCN-1 

X0001 = SRC 1 

X0010 = SRC 2 

X001 1 = SRC 3 

X0100 = SRC 4 

X0101 = SRC 5 

X0110 = GATE 1 

X0111 = GATE 2 

X10OO = GATE 3 

X1001 = GATE 4 

X1010 = GATE 5 

X1011 = F1 

X1100 = F2 

X1101 - F3 

X1110 = F4 

X1 11 1 = F5 . 



{— Count Control 

OXXXX = Disable Special Gate 
1XXXX = Enable Special Gale 
XOXXX = Reload from Load 
X1XXX = Reload from Load or Hold 
XX0XX = Count Once 
XX1XX = Count Repetitively 
XXX0X = Binary Count 
XXXIX = BCD Count 
XXXX0 = Count Down 
XXXX1 = Count Up 



CM15 


CM14 


CM13 


CM12 


CM11 


CM10 


CM9 


CM8 


CM7 



CM6 

— i 


CMS 




CM4 



CM3 


CM2 


CM1 


CMO 



r 



Gating Control 

000 - No Gating 

001 = Active High Level TCN-1 

010 = Active High Level GATE N + 1 

011 - Active High Level GATE N-1 

100 = Active High Level GATE N 

101 = Active Low Level GATE N 

110 = Active High Edge GATE N 

1 1 1 =• Active Low Edge GATE N 



Output Control 

000 = Inactive. Output Low 

001 = Active High Terminal Count Pulse 

010 = TC Toggled 

01 1 - Illegal 

100 = Inactive. Output High Impedance 

101 * Active Low Terminal Count Pulse 

110 = Illegal 

111 - Illegal 



Note: See Figure 17 lor restrictions on Count Conirol and Gating Contol bit combinations. 



Figure 18. Counter Mode Register Bit Assignments. 



Am9513 



tOW 2 TO 
CflOUNO/MKiM 
I CONTROL 



INTERNAL TC 
■ CONNECTION TO 
ADJACENT COUNTER 



COUNTERS 1 AND 3 OMLY 



Figure 19. Output Control Logic. 



The toggle output is 1/2 the frequency ot TC. The TC Toggled 
output will frequently be used to generate variable duty-cycle 
square waves in Operating Modes G through K. 
In Mode L the TC Toggled output can be used to generate a 
one-shot function, with the delay to the start ot the output pulse 
and the width of the output pulse separately programmable. With 
selection of the minimum delay to the start ol the pulse, the output 
;.-.!'. Jijjfe or, n euun* puise lonowing application ol the trig- 
gering Gate edge. 

Note that Ihe TC Toggled output form contains no implication 
about whether the output is active-high or active-low. Unlike the 
TC output, which generates a transient pulse which can clearly be 
active-high or active-low. the TC Toggled output wavelorm only 
flips the state of the output on each TC. The sole criteria ol 
whether the TC Toggled output is active-high or active-low is the 
level of the output at the start of the count cycle. This can be 
controlled by the Set and Clear Output commands. 
TC (TERMINAL COUNT) 

On each Terminal Count (TC). the counter will reload itselt Irom 
Ihe Load or Hold register. TC is defined as that period of time 
when the counter contents would have been zero had no reload 
occurred. Some special conditions apply to counter operation 
immediately before and during TC. 

I. In the clock cycle before TC, an internal signal is generated 
thai commits the counter to go to TC on the next count, and 
retriggering by a hardware Gate edge (Modes N, O. Q and R) 
or a software LOAD or LOAD-and-ARM command will not 
extend the time to TC. Note that the -next count" driving the 
counter to TC can be caused by the application of a count 



source edge (in level gating modes, the edge must occur white 
the gate is active, or it will be disregarded), by the application 
ol a LOAD or LOAD-and-ARM command (see 2 below) or by 
the application ol a STEP command. 

2. Jf a LOAD or LOAD-and-ARM command is executed during 
the cycle preceding TC, Ihe counler will immedialely go to TC. 
If these commands are issued during TC, the TC state will 

iiiimeiiidieiy leiminaie. 

3. When TC is active, the counter will always count the next 
source edge issued to it. even if it is disarmed or gated oft 
during TC. This means that TC will never be active for longer 
than one count period and it may, in tact, be shorter if a STEP 
command or a LOAD or LOAD-and-ARM command is applied 
during TC (see item 2 above). This also means that a counter 
lhat is disarmed or stopped on TC is actually disarmed/ 
stopped immediately following TC. 

This may cause count sequences dilterent from what a user might 
expect. Since the counter is always reloaded at the start of TC, 
and since it always counts at the end ol TC, the counter contents 
following TC will differ by one Irom the reloaded value, irrespec- 
tive of the operating mode used. 

If the reloaded value was 0001 for down counting, 9999 (BCD) for 
BCD up counting or FFFF (hex) for binary up counting, the count 
at the end of TC will drive the counter into TC again regardless of 
whether ihe counter is galed off or disarmed. As long as these 
values are reloaded, the TC output will slay active. K a TC Tog- 
gled outpul is selected, it will toggle on each count. Execution of a 
LOAD, LOAD-and-ARM or STEP command with these counter 
contents will act the same as application of a source pulse, 
causing TC to remain active and a TC Toggled output to toggle. 



J V_ 



J ^ !(— 



Figure 20. Counter Output Waveforms. 



Count Control 

Counter Mode bits CMS through CM7 specify the various options 
available lor direct control o( the counting process. CM3 and CM4 
operate Independently o( the others a.nd control up/down and 
BCD/binary counting. They may be combined Ireely with olher 
control bits to kxm many types of counting configurations. The 
other three bits and the Gating Control field Interact in complex 
ways. Bit CM5 controls the repetition ol the count process. When 
CM5 - 1, counting will proceed in the specified mode until the 
counter Is disarmed. When CM5 - 0, the count process will 
proceed only una one lull cycle of operation occurs. This may 
occur after one or two TC events. The counter Is then disarmed 
automatically. The single or double TC requirement will depend 
on the state of other control bits. Note that even II the counter Is 
automatically disarmed upon a TC, it always counts the count 
source edge which generates the trailing TC edge. 
When TC occurs, the counter is always reloaded with a value 
from either the Load register or .the Hold register. Bit CM6 
specifies the source options lor reloading the counter. When CM6 
> the contents of the Load register will be transferred into the 
counter at every occurrence of TC. When CMS - 1, the counter 
reload location win be ilther the Load or Hold Register. The 
reload location in this case may be controlled externally by using 
a GATE pin (Modes S and V) or may alternate on each TC (Modes 
G through L). Wilh alternating sources and with the TC Toggled 
output selected, the duty cycle of the output waveform is control- 
led by Ihe relative Load and Hold values and very line resolulion 

nl H,,lw r^lA r«t^» may K« 

Bit CM7 controls the special gating functions that allow retrigger- 
ing and the selection of Load or Hold sources lor counter reload- 
ing. The use and definition of CM7 will depend on the status ol the 
Gating Control field and bits CMS and CM6. 
When some lotm of Gating is specified. CM7 controls hardware 
retriggering. In Ihis case, when CM7 - hardware retriggering 
does not occur; when CM7 = 1 1he counter is retriggered any time 
an active-going Gale edge occurs. Retriggering causes the 
counter value lo be saved in the Hold register and the Load 
register conlents to be transferred into the counter. 
Whenever hardware retriggering is enabled (Modes N, O. Q and 
R) all active going Gate edges initiate retrigger operations. On 
application of Ihe Gale edge, the counter contents will be transfer- 
red to the Hold register. On the first qualified source edge after 
application of Ihe retriggering Gate edge, the Load register con- 
tents will be transferred inlo the counter. (Qualified source edges 
are edges which occur while the counter Is gated on and Armed.) 
This means that if level gating Is used, the edge occurring on 
active-going gate transitions will initiate a retrigger. Similarly, 
when edge gating is enabled, an edge used to start the counter 
will also initiate a retrigger. The first count source edge applied 
after the Gate edge will not increment/decrement the counter but 
reload it. 

When No Gating is specified. Ihe definition of CM7 changes. In 
this case, when CM7 - Ihe Gale input has no effect on the 
counting: when CM7 - 1 the GATE N input specifies the reload 
source (either Ihe Load or Hold register) used lo reload the 
counler when TC occurs. Figure 17 shows the various available 
control combinations for Ihese interrelaled oils. 

Count Source Selection 

Counler Mode bits CM8 through CM12 specify the source used as 
input lo the counter and the active edge that Is counted. Bit CM1 2 
controls Ihe polarity for all the sources; logic zero counts rising 
edges and logic one counts falling edges. Bits CMS through CM1 1 
select 1 of 16 counting sources to route to Ihe counter input. Five 



ol Hit available inputs are internal frequencies derived from the 
internal oscillator (see Figure 16 lor frequency assignments). Ten 
ol the available inpuls are interlace pins; five are labeled SRC and 
five are labeled GATE. 

The 16th available input is the.TC oulput from the adjacent 
lower-numbered counter. (The Counter 5 TC wraps around to the 
Counter 1 Input.) This option allows Internal concatenating that 
permits very long counts lo be accumulated. Since all live count- 
ers may be concatenated. It Is possible lo configure a counler that 
is 80 bits long on one Am9513 chip. When TON- 1 is the source. 
Ihe count ripples between the connected-counters. External con- 
nections can also be made, and can use the toggle oil lor even 
longer counts. This is easily accomplished by selecting a TC 
Toggled output mode and wiring OUTN lo one of the SRC inputs. 

Gating Control 

Counler Mode bits CM13 through CM15 specify the hardware 
gating options. When "no gating" is selected (000) the counler 
will proceed unconditionally as long as it is armed. For any other 
gating mode, the count process is conditioned by Ihe specified 
gating configuration. 

For a code of 100 in this field, counting can proceed only when the 
pin labeled GATEN associated wilh Counler N is al a logic high 
level. When it goes low. counting is simply suspended until the 
Gale goes high again. A code of 101 performs the same function 
wilh an opposile active polarity. Codes 010 and 011 offer the same 
function as 100, but specify alternate input pins as Gating 
Cm.r« TWt ,n™.«. ~* i"'.crf~cc pi" '.c be -jcci zz 
gales lor a given counler. On Counter 4. lor example, pin 34. pin 
35 or pin 36 may be used lo perform Ihe galing lunclion. This also 
allows a single Gate pin lo simultaneously control up lo three 
counters. 

For codes ol 110 or 111 in Ihis lield. counting proceeds after Ihe 
specified active Gate edge until one or two TC events occur. 
Within Ihis interval the Gale input is ignored, excepl for the 
retriggering option. When repetition is selected, a cycle will be 
repealed as soon as another Gate edge occurs. With repetition 
selected, any Gale edge applied after TC goes active will start a 
new count cycle. Edge gating is useful when implemenling a 
digilal single-shot since ihe gale can serve as a convenienl 
firing trigger. 

A 001 code in Ihis lield -selects the TC oulput Irom the adjacent 
lower-numbered counler as the gate. Thus, one counler may be 
configured lo generate a counting "window" lor anolher counler. 



COMMAND DESCRIPTIONS 

The command set lor Ihe Am9513 allows Ihe host processor lo 
customize and manage the operating modes and features lor 
particular applications, lo initialize and updale both the internal 
dala and control information, and lo manipulale operaling bits 
during operalion. Commands are entered directly inlo ihe B-bil 
Command register by wriling inlo Ihe Conlrol port (see Figure 7). 
All available commands are described in Ihe following lexl. Figure 
21 summarizes Ihe command codes and includes a brief descrip- 
lion ol each lunclion. Figure 22 shows all Ihe unused code oombi- 
nalions; unused codes should nol be entered inlo Ihe Command 
register since undefined activities may occur. 
Six ol Ihe command types are used lor direct software conlrol ol 
ihe counting process and they each conlain a 5-bit S field. In a 
linear-select (ashion. each bit in the S field corresponds lo one ol 
the live general counters (SI - Counler 1 . S2 - Counler 2, etc.). 
When an S oil is a one. Ihe specified operalion is pertormed on 
Ihe counter so designated; when an S oil is a zero, no operalion 



Am9513 



Command Code 


: 

Command Description 


C7 


C6 


CS 


C4 


C3 


C2 


CI 


CO 




o 


o 


E2 


f£| 


G4 


G2 


G1 


Load Data Pointer register wilh contents ol E and G fields. 
(G j< 000. G ? 110) 








1 


SS 


S4 . 


S3 


S2 


SI 


Arm counting lor all selected counters 





1 





S5 


S4 


S3 


S2 


S1 


Load contents ol specified source into all selected counters 





1 


1 


S5 


S4 


S3 


S2 


S1 


Load and Arm an selected counters 










S5 


S4 


S3 


S2 


S1 


Disarm and Save all selected counters 







1 


S5 


S4 


S3 


S2 


S1 


Save all selected counters in hold register 


1 


1 





S5 


S4 


S3 


S2 


S1 


Disarm all selected counters 


1 


1 


1 





- 1 


N4 


N2 


N1 


Set output bit N (001 * N < 101) 


1 


1 


1 








N4 


N2 


N1 


Clear output bit N (001 s N < 101) 




1 


1 


1 





N4 


N2 


N1 


Step counler N (001 « N « 101) 




1 


1 





1 











Set MM14 (Disable Dala Pointer Sequencing) 




1 


1 





1 


1 


1 





Set MM 12 (Gale oil FOUT) 




1 


1 





1 


1 


1 


1 


Set MM13 (Enter 1 6-bit bus mode) 




1 


1 

















Clear MM14 (Enable Dala Pointer Sequencing) 




1 


1 








1 


1 





Clear MM12 (Gale on FOUT) 














" 1 


1 


Clear MM13 (Enter B-bil bus mode) 


1 


1 


1 


1 


1 




1 


1 


Master reset 



Figure 21. Arn9513 Command Summary. 



occurs lor the corresponding counter. This type of command 
format has three basic advantages. ft saves host software by 
allowing any combination of counters to be acted on by a single 
command. It allows simultaneous action on multiple counters 
where synchronization of commands is important. It allows 
counter- specific service routines to conlrol individual counters 
without needing to be aware of the operating context of other 
counters. 



Arm Counters 



Coding: 



C7 


C6 


CS 


C4 


C3 


C2 


C1 


CO 








1 


S5 


S4 


S3 


S2 


S1 



Description: Any combination of counters, as specified by the S 
field, will be enabled for counting. A counter must be armed 
before counting can commence. Once armed, the counting pro- 
cess may be further enabled or disabled using the hardware 
gating facilities. This command can only arm or do nothing for a 
given counter; a zero in the S field does not disarm the counter. 

ARM and DISARM commands can be used to gale counter 
operation on and off under software control. DISARM commands 
entered while a counter is in the TC state will not take effect untH 
the counter leaves TC. This ensures that the counter never 
latches up in a TC state. (The counter may leave the TC state 
because of application of a count source edge; execution of a 
LOAD or LOAD-and-ARM command: or execution of a STEP 
command.) 

In modes which alternate reload sources (Modes G-L). the 
ARMing operation is used as a reset for the logic which deter- 
mines which reload source to use on the upcoming TC. Following 



each ARM or LOAD-and-ARM command, a counter in one of 
these modes will reload Irom the Hold register on the first TC and 
alternate reload sources thereafter (reload from the Load register 
on the second TC. the Hold register on the third, etc.). 

In edge gating modes (Modes C. F, I. L. O and R) after disarming 
and rearming a triggered counter, a new Gate edge will be 
required to resume counting. In Modes C, F. I and L counting will 
resume from the current counter value. In modes O and R the 
new Gate edge will both start and retrigger the counter, causing 
the counter to be reloaded with a new value. 



Load Counter* 



C7 


C6 C5 


C4 


C3 


C2 


C1 


CO 





1 


S5 


S4 


S3 


S2 


SI 



Description: Any combination of counters, as specified in the S 
field, will be loaded with previously entered values. The source of 
information for each counter will be either the associated Load 
register or the associaled Hold register, as determined by the 
operating configuration in the Mode register. The Load/Hold 
contents are not changed. This command will cause a transfer 
independent of any current operaling configuration lor the 
counter. It will often be used as a software retrigger, or as counter 
initialization prior to active hardware gating. 

If a LOAD or LOAD-and-ARM command is executed during the 
cycle preceding TC, the counter will go immediately to TC. This 
occurs because the LOAD operation is pertormed by generating 
a pseudo-count pulse, internal to the Am9513, and the Am9513 is 
expecting to go into TC on the next count pulse. The reload 



Am9513 



> 

I 



source used to reload the counter will be the same 35 thot which 
would have been used il ihe TC were generated by a source 
edge rather than by the LOAD operation. 
Execution ol a LOAD or LOAD-and-ARM command while a 
counter is in TC will cause the TC to end. For Armed counters in 
all modes except S or V. Ihe reload source used will be that to be 
used lor the upcoming TC. (The LOADing operation will no! alter 
Ihe selection of reload source for the upcoming TC.) For Dis- 
armed counters in modes except S or V.the reload sources used 
will be the LOAD register. For modes S or V, the reload source 
will be selected by the GATE input, regardless ol whether Ihe 
counter is Armed or Disarmed. ' • ■ ■ 
Special considerations apply when modes with alternating re- 
load sources are used (Modes G-L). H a LOAD command drives 
the counter 10 TC in these modes, the reload source lor the next 
TC will be from the opposite reload location. In other words, the 
LOAD-generated TC will cause the reload sources 10 alternate 
Just as a TC generated by a source edge would. Note that il a 
second LOAD command is issued during the LOAD-generated 
TC (or during any other TC, lor that matter) the second LOAD 
command will terminate the TC and cause a reload Irom the 
source designated for use with the next TC. The second LOAD 
will not alter the reload source lor the next TC since Ihe second 
LOAD does not generate a TC; reload sources alternate on TCs 
only, not on LOAD commands. 



Load and Arm Counter* 



Save Counters 



Coding: 



C7 C6 C5 


C4 


C3 


C2 


CI 


co 


1 1 


S5 


S4 


S3 


S2 


S1 



Description: Any combinalion ol counters, as specified in the S 
field, wffl be first loaded and then armed. This command is 
equivalent to issuing a LOAD command and then an ARM 
command. 

A LOAD-and-ARM command which drives a counter to TC gen- 
erates the same sequence of operations as execution of a LOAD 
command and then an ARM command. In modes which disarm 
on TC (Modes A-C and N-O, and Modes G-l and S if the current 
TC is the second in the cycle) the ARM part of the LOAD-and- 
ARM command will re-enable counting lor another cycle. In 
modes which alternate reload sources (Modes G-L) the ARMing 
operating will cause the next TC to reload from the HOLD regis- 
ter, irrespective of which reload source the current TC used. 



Disarm Counter* 



Coding: 



C7 C6 C5 


C4 


C3 


C2 


CI 


CO 


1 1 


SS 


S4 


S3 


S2 


St 



Description: Any combination of counters, as specified by the S 
field, will be disabled from counting. A disarmed counter will 
cease all counting independent of other control condrttons, The 
only exception to this is that a counter in the TC state will always 
count once, in order to leave TC. before DISARMing. This count 
may be generated by a source edge, by a LOAD or LOAD-and- 
ARM command (the LOAD-and-ARM command will negate the 
DISARM command) or by a STEP command. A disarmed 
counter may be updated using the LOAD command and may be 
read using the SAVE command. A count process may be re- 
sumed using an ARM command. See the ARM command de- 
scription for further details. 



Coding: 


C7 C6 C5 C4 


C3 


C2 


CI CO 




1 1 S5 


S4 


S3 


S2 St 



Description: Any combination ol counters, as specified by the S 
field, will have Iheir contents transferred into their associated . 
Hold register. The transfertakes place without interfering with any 



counting that may be underway. This command will overwrite any 
previous Hold register contents. The SAVE command is de- 
signed to allow an accumulated count to be preserved so that it 
can be read by the host CPU at some later time. 

Disarm and Save Counters' 



Coding: 



C7 C6 


C5 C4 


C3 


C2 


C1 


CO 


1 


S5 


S4 


S3 


S2 


SI 



Description: Any combination of counters, as specified by Ihe S 
lield. will be disarmed and the contents of the counter will be 
transferred into Ihe associated Hold registers. This command is 
identical to issuing a DISARM command followed by a SAVE 
command. 

Set Output 

Coding: j C7 C6 C5 C4 C3 C2 C1 CO j 

I 1 1 i i uz r." | 

(001 < N « 101) 

Description: The output toggle lor counter N is set. The OUTN 
signal will be driven high unless a TC output is specified. 

Clear Output 



Coding: 


C7 C6 C5 C4 


C3 


C2 C1 


CO 




1110 





N4 N2 


N1 



(001 « N < 101) 

Description: The output toggle lor counter N is reset. The OUTN 
signal will be driven low unless a TC output is specified. 



Step Counter 

Coding: 



C7 


05 


C5 


C4 


C3 C2 


C1 


CO 


1 


1 


1 


1 


N4 


N2 


N1 



(001 * N < 101) 
Description: Counter N is incremented or decremented by one, 
depending on its operating configuration. If the Counter Mode 
register associated with the selected counter has its CM3 bit 
cleared to zero, this command wiH cause the counter to decre- 
ment by one. If CM3 is set to a logic high, this command will 
increment the counter by one. The STEP < 
effect even on a disarmed counter. 

Load Data Pointer Register 



C7 


C6 


C5 


C4 


C3 


C2 


C1 


CO 











E2 


E1 


G4 


G2 


G1 



(G4.G2, G1 ? 000. i* 110) 
Description: Bits in the E and G fields will be transferred into the 
corresponding Element and Group fields of the Data Pointer 



Arr,9513 



register as shown in Figure 6. The Byte Pointer oil in me Data 
Pointer register is set. Transfers into the Data Pointer only 
occur lor G field values of 001. 010, 011. 100, 101 and 111. 
Values ol 000 and 1 10 for G should not be used. See the "Setting 
the Dala Pointer Register" section of this document lor additional 
details. ■ 



Gate Otf FOUT 

Coding: 



C7 CS C5 C* C3 C2 CI CO 



Disable Data Pointer Sequencing 

Coding: 



C7 C6 C5 


C4 


C3 


C2 


C1 


CO 


1 1 1 





1 












Description: This comma/id sets Master Mode bit 12 without 
affecting other bits In the Master Mode register. MM1 2 controls 
the output stole ol the FOUT signal. When gated off. the FOUT 
line will exhibit a low impedance to ground. MM 12 may also be 
controlled by loading Ihe full Master Mode register In parallel. 



Gate On FOUT 



Description: This command sets Master Mode bit 14 without 
affecting other bits in the Master Mode register. MM14 controls 
the automatic sequencing of the Data Pointer register. Disabling 
the sequencing allows repetitive host processor access to a given 
internal location without repetitive updating of the Data Pointer. 
MM 14 may also be controlled by loading a full word into the 
Master Mode register. 



Enable Data Pointer Sequencing 

Coding: 



C7 C6 C5 C4 C3 C2 C1 CO 



Description: This command clears Master Mode bit 14 without 
affecting other bits in the Master Mode register. MM14 controls 
the automatic sequencing of the Dala Pointer register. Enabling 
the sequencing allows sequential host processor access to sev- 
eral internal locations without repetitive updating of the Dala 
Pointer. MM14 may also be controlled by loading a full word into 
the Master Mode register. See the "Data Pointer Register" sec- 
lion of this document for additional information on Data Pointer 
sequencing. 



Enable 16-Bit Data Bus 



Coding: 



C7 C6 C5 C4 , C3 C2 C1 CO 



1 



1 



1 



Description: This command sels Master Mode bit 13 without 
affecting other bits in the Master Mode register. MM13 controls 
the multiplexer in the data bus buffer. When MM 13 is set. no 
multiplexing takes place and all 16 external data bus lines are 
used lo transfer information into and out of the STC. MM13 may ' 
also be controlled by loading the full Master Mode register in 
parallel. 



Enable 8-Blt Data Bus 



Coding: 



C7 C6 C5 C4 C3 C2 C1 CO 



Description: This command clears Master Mode bit 13 without 
affecting other bits in the Master Mode register. MM 13 controls 
Ihe multiplexer in the data bus buffer. When MM 13 is cleared, the 
multiplexer is enabled and 16-bit internal information is trans- 
ferred eight bits at a time to the eight low-order external dala bus 
lines. MM 13 may also be controlled by loading the lull Master 
Mode register in parallel. 



Coding: 



C7 C6 C5 C4 


C3 


C2 C1 


CO 


1110 





1 1 






Description: This command clears Master Mode bit 12 without 
affecting other bits In the Master Mode register. MM12 controls 
the output status of the FOUT signal. When MM12 is cleared, 
FOUT will become active and will drive out the selected and 
divided FOUT signal. MM1 2 may also be controlled by loading the 
lull Master Mode register in parallel. When FOUT Is gated on or 
off, a transient pulse may be generated on the FOUT signal. 

Master Reset 



Coding: 



C7 


C6 


C5 


C4 


C3 


C2 


Cl 


CO 


1 


1 


1 


1 


1 


1 


1 


1 



Description: The Master Reset command duplicates the action 
ol the power-on reset circuitry. H disarms all counters, enters 
0000 in the Master Mode. Load and Hold registers and enters 
0800 (hex) in the Counter Mode registers. 

Following either a power-up or software reset, the LOAD com- 
mand should be applied lo all Ihe counters to clear any that may 
be in a TC state. The Dala Pointer register should also be set to a 
legal value, since reset does not initialize t A complete reset 
operation is given in the following. 

1. Using the procedure given in the "Command Initiation" sec- 
tion ol this data sheet, enter Ihe FF (hex) command to perform 
a software reseL 

2. Using Ihe "Command Initiation" procedure, enter the LOAD 
command lor all counters, opcode 5F (hex). 

3. Using the procedure given in the "Setting the Dala Pointer 
Register" section of this data sheet, set the Data Pointer lo 
a valid code. The legal Data Pointer codes are given in 
Figure 9. 

The Master Mode, Counter Mode. Load and Hold registers can 
now be initialized to the desired values. 



C7 


CS 


CS 


C4 


C3 


C2 


C1 


CO 


1 


1 


1 


1 











0. 


1 


1 


1 


1 





1 


1 





1 


1 


1 


1 





1 


1 


1 











X 


X 


1 


1 














X 


X 











1 


1 


1 


1 


1 


X 


X 


X 



*Unu*«<J •xcep* wh»n XXX "111. / 

Figure 22. Am9513 Unused Command Codes. 



Am9513 




MAXIMUM RATINGS beyond which uselul Hie may be impaired 




Storage Temperature 


-6S*C lo +150"C 


Ambient Temperature Under Bias 


-55'Cto +125X 


VCC with Respect lo VSS 


-0.5V to +7.0V 


All Signal Voltages with Respect to VSS 


-0.5V to + 7.0V- 


Power Dissipation (Package Limitation)' 


1.5W 



The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of 
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid 
exposure to excessive voltages. 



OPERATING RANGE 



Part Number 


Temperature 


VCC 


VSS 


Am95130C 


o-c « T A < +70-C 


+ 5V 15% 


ov 


Am9S13DM 


-55-C < T A < +125-0 


+ 5V 15% 


ov 



ELECTRICAL CHARACTERISTICS over operating range (Notes 1 and 2) 



Parameter 


Description 


Test Conditions 


Mln 


Typ 


Max 


Units 






All tnpuls Except X2 




VSS -0.5 1 


O.fi 








X2 Input 




VSS -0.5 




0.8 


Volts 


VIH 


Input High voltage 


All Inputs Except X2 




2.0 




VCC 


VcJts 


X2 Input 




3.4 




vcc 


VITH 


Input Hysteresis (SRC and GATE Inputs Only) 




0.2 


3 




Volts 


VOL 


Output Low Voltage 


IOL - 3.2mA 






0.4 


Volts 


VOH 


Output High Voltage 


IOH - -200fiA 


2.4 






Volts 


IOH - -1.5mA 


1.5 






HX 


Input Load Current (Except X2) 


VSS < VIN < VCC 






= 10 


*A 


m 


Output Leakage Current (Except XI) 


VSS « VOUT < VCC 
High Impedance State 






= 25 










T A - -55-C 






275 




ICC 


VCC Supply Current 




T A - 0-C 






225 


mA 








T A - +25-C 




160 






CIN 


Input Capacitance 


I - 1MHz, T A - *25-C. 






10 




COUT 


Output Capacitance 


Alt pins not under 






15 




CIO 


IN/OUT Capacitance 


lest a! OV. 






20 





A 



Am9513 




FN. 1 



X 



Figure 24. Counter Switching Waveforms. 



uos ie* 



Am9513 

SWITCHING CHARACTERISTICS over opening range (Noies 2, 3, 4) 



Parameter 


Descrlplk 


n 


Figure 


Mln 


Max 


Mln 


Max . 


Units 


TAVRL 


C/D Valid 10 Read Low 


23 


25. 








nsj 


TAVWH 


C/D Valid lo wme High • 


23 


170 










ns 


TCHCH 


X2 High to X2 High (X2 Period) 


24 


145 








ns 


TCHCL 


X2 High lo X2 Low (X2 High Pulse Width) • - 




70 - 










TCLCH 


X2 Low lo X2 High (X2 Low Pulse Widlh) 


24 


70 










TDVWH 


Dala In Valid lo Wrlle High 
















Court Source High lo Count Source High (Source Cycle Time) (Note 10) 














TEHEL 
TELEH 


Count Source Pulse Deration (Note 10) 


24 


-TO 








ns 


TEHFV - 


Court Source High lo FOOT Valid (Note 10) 


24 




500 








TEHGV 


Count Source High to Gale Valid (Level Gating Hold Time) 
(Notes 10. 12. 13) 


24 


40 








ns 


TEHRL 


Count Source High lo Read Low (Set-up Time) (Notes 5, 10) 


23 


190 










TEHWH 


Count Source High lo Write High (Set-up Time) (Notes 6, 10) 


23 


100 














TC Output 


24 




300 








TEHYV 


Court Soiree High to Out Valid (Note 10) 


Immediate Of Delayed Toggle Output 


24 




300 






ns 






Comparator Output 


24 




350 








TEN 


FN High lo FN + 1 Valid (Note 14) 


24 




75 






ns 


TGVEH 


Gale Valid to Counl Source High (Level Gating Sel-up Time) 


?4 


70 




























TGVGV 


Gale Valid lo Gale Valid (Gate Pulse Duralion) (Notes 11. 13) 


24 


145 








ns 


TGVWH 


Gate Valid to Write High (Noles 6. 13) 


23 











ns 


TRHAX 


Read High 10 C/D Don ! Care 


23 











ns 


TRHEH 


Read High lo Counl Source High (Notes 7. 10) 


23 











ns 


TRHQX 


Read High lo Dala Out Invalid 


23 


20 








ns 




Read High lo Dala Out at High Impedance 
(Data Bus Release Time) 














TRHRL 


Read High lo Read Low (Read Recovery Time) 


23 




1000 






ns 


TRHSH 


Read High 10 CS High (Nole 15) 


23 











ns 


TRHWL 


Read High to Write Low (Read Recovery Time) 


23 




1000 






ns 


TRLOV 


Read Low lo Dala Out Valid 


23 




160 






ns 


TRLQX 


Read Low lo Data Bus Driven (Data Bus Drive Time) 


23 


20 








ns 


TRLRH 


Read Low to Read High (Read Pulse Duralion) (Note 15) 


23 


160 








ns 


TSLRL 


CS Low lo Read Low (Nole 15) 


23 


20 








ns 


TSLWH 


CS Low to Wnle High (Note 15) 


23 


170 








ns 


TWHAX 


Write High lo C/D Don! Care 


23 











ns 


TWHDX 


Write High to Deta In Donl Care 




23 











ns 


TWHEH 


Write High lo Count Source High (Notes 8. 10. 17) 


23 


400 








ns 


TWHGV 


Write Hign lo Gale Valid (Noles 8, 13, 17) 


23 


400 








ns 


TWHRL 


Write High lo Read Low (Write Recovery Time) 


23 




1000 






ns 


TWHSH 


Write High to CS High (Nole 15) 


23 











ns 


rwHwi 


Write High lo Write Low (Write Recovery Time) 


23 




10O0 






ns 


TWHYV 


Write High lo Oul Valid (Note 9. 17) 


23 




650 






ns 


] TWLWH 


Write Low lo Wrile High (Wile Pulse Duralion) (Nole 15) 


23 


150 


1 




na 



Am9513 



NOTES: 

1. Typical values are for T A = 25"C, nominal supply voltage 
and nominal processing parameters. 

2 Test conditions assume transition times o( 10ns or less, 
timing reference levels 0IO.8V and 2.0V and output loading 
of one TTL gate ptus lOOpf. unless otherwise noted. 

3. Abbreviations used for the switching parameter symbols are 
given as the letter T followed by four or five characters. The 
first and third characters represent the signal names on 
which the measurements start and end. Signal abbrevia- 
tions used are: 

A (Address) « 00 

C (Clock) m X2 

D (Data In) - DB0-DB15 

E (Enabled counter source input) » SRC1-SRC5. 

GATE1-GATE5. F1-F5. TCN-1 
F - FOUT 

G (Counter gate input) - GATE1-GATE5, TCN-1 

Q (Data Out) - DB0-DB15 

R (Read) = RO 

S (Chip Select) - CS 

W (Write) - WR 

Y (Output) = OUT1-OUT5 

The second and fourth letters designate the reference 
states of the signals named in the first and third letters 

reSOflCtivfilv U<inn the* fnllnwinn ahhi-o^ati^rn: 

H = High 
L = Low 

V «= Valid 

X = unknown or don't care 
2 = high impedance 

4. Switching parameters are listed in alphabetical order. 

5. Any input transition that occurs belore this minimum setup 
requirement will be reflected in the contents read from the 
status register. 

6. Any input transition that occurs before this minimum setup 
requirement will act on the counler before the execution of 
the operation initiated by the write. Failure to meet this setup 
time when issuing commands to the counter may result in 
incorrect counter operation. 



7. Any input transition that occurs after this minimum hold time 
is guaranteed to not influence the contents read Irom the 
status register on the current read operation. 

8. Any input transition that occurs after this minimum hold time 
Is guaranteed to be seen by the counter as occurring after the 
action initiated by the write operation. Failure to meet this 
hold time when issuing commands to the counter may result 
in incorrect counter operaiion. 

9. This parameter applies to cases where the write operation 
causes a change in the output bit. 

10. The enabled count source Is one of F1-F5, TCN-1, 
SRC1-SRC5 or GATE 1 -GATE 5, as selected in the applica- 
ble Counter Mode register. The timing diagram assumes 
the counter counts on rising source edges. The timing spec- 
ifications are the same for latling-edge counting. 

11. This parameter applies to edge gating (CM15-CM13 - 110 
or 111) and gating when both CM7 m 1 and CM15-CM13 f 
000. This parameter represents the minimum GATE pulse 
width needed to ensure that the pulse initiates counting or 
counter reloading. 

12. This parameter applies to both edge and level gating 
(CM15-CM13 - 001 through 111) and gating when both CM7 
■ 1 and CM15-CM13 - 000. This parameter represents the 
minimum setup or hold times to ensure that the Gate input is 
seen at the intended level on the active source edge. Failure 
to met the required setup and hold times may result in 
incorrect counter operation. 

i j. 1 nis parameter assumes mat the GAl tNA input is unused 
(16-bit bus mode) or is tied high. In cases where the 
CATENA input is used, this timing specification must be met 
by both the GATE and GATENA inputs'. 

14. Signals F1-F5 cannot be directly monitored by the user. The 
phase difference between these signals will manifest itself 
by causing counters using two different F signals to count at 
different times on nominally simultaneous transitions in the 
F signals. 

15. This timing specification assumes that CS is active 
whenever RD or WR are active. CS may be held active 
indefinitely. 

16. This parameter assumes X2 is driven from an external gate 
with a square wave. 

17. This parameter assumes that the write operation is to the 
command renter. 



Am9513 



APPLICATION INFORMATION 

The X1 and X2 inputs can be driven with a RC network, an 
external TTL-level square wave, or a crystal. Figure 25 shows 
the suggested methods ol connecting dilterent trequency 
sources to the internal oscillator input. 

The use ol a crystal provides a highly accurate trequency source 
at moderate cost, and accordingly, will usually be the preferred 
method of operation. The Am9513 is designed to use a crystal in a 
parallel-resonant mode. The two ceramic capacitors connecting 
X1 and X2 to ground ensure proper loading on the crystal. The 
capacitor to. X2 may be an adjustable type lor tine-tuning the 
resonant frequency (*.-; critical applications. 

An RC network provides a very low cost frequency source but 
may exhibit large frequency variations over recommended 
power supply and temperature ranges. Note that there Is a re- 
sistor internal to the Am9513 in parallel with any external 
resistance. 

Initialization Procedures 

The reset lunction in the Am9513 is accomplished in two 
ways: automatically during power-up and by software Master 
Reset command. Power-up reset circuitry is internally triggered 
by the rising VCC voltage when a predetermined threshold is 
reached. An internal flip-flop is set by the rising supply voltage 
and control^ the reset operation. The reset flip-flop remains set 
until cleared by the first active Chip Select input. A reset may also 

bV initialed DV the host DtOcessnr hv enlprirvi Iho Uaclw Qocot 

command. This software reset is active for the duration of the 
command write; otherwise it performs the same function as the 
power-up reset. 



Following either type ol Reset, all five counters are disabled. 
0B00 is loaded into each Counter Mode register, and 0000 is 
loaded in the Masler Mode register. This results in each counter 
being configured lo counl down in binary on the positive-going 
edge ol the internal Fl Irequency source with no repetition or 
gating. The Master Mode register is cleared to configure the* 
Am9513 for an 8-bit data bus width; binary division of the internal 
oscillator, FOUT galed on and set to divide Fl by 16; lime-ol-day ■ 
mode and comparators 1 and 2 disabled: and the Data Pointer 
increment enabled. 

Reset will clear the Load and Hold registers for each counter but 
will not change either the counter contents or the Data Pointer 
register. .Following a reset, the "Load All Counters" command 
(opcode 5F hex) should be issued to clear any counters that may 
be at TC. The Masler Mode and Counter Mode, Load and Hold 
registers may now be set. 

1 . Set Time-of-Oay enabled in the Master Mode register and load 
Counter Mode registers 1 and 2. 

2. If Time-ol-Day is lo count up, load 0000 in Load registers 1 and 
2 and execute command FF43 (Load) to load this value into 
the counters. This step conditions the count circuitry. 

3. Load Ihe desired start time into the Load registers and execute 
command FF43 again. 

4. For counting up, load Load reqisters 1 and 2 with 0000. 

5. Counters 1 and 2 may now be armed. 



QBX-TMR 



Appendix B: Appl ications 



APPENDIX B 
APPLICATIONS 



General 

As with all timer/coun ;ers the QBX-TMR may be used to time 
certain intervals and count events albeit with a large degree of 
flexibilty with gates and allowing dynamic changes of souces and 
gates of particular counter. The QBX-TMR also allows operation as 
an FSK signal generator, which is covered in the AMD data sheet 
in Appendix A. 



A Frequency Counter 

The frequency output is fed into one of the counters via a source 
input. This counter is set up in mode B, so that it will only 
count whilst its gate is high. A second counter is configured in 
mode G, with the load counter set to 2 (note: it cannot be set to 
1 as erratic operation occurs) and the hold register set to the 
timing period say 250 milliseconds. The output of this second 
gate (set in the toggled mode) is fed to the gate of the first 
counter. These two gates are now configured as a frequency 
counter. Counting begins under software initiaion. 

An Analogue to Digital Converter 

The QBX-TMR may be used to replace an analogue to digital 
converter under certain circumstances. The output of the 
transducer as a voltage or a current is fed into a voltage to 
frequency converter such as the Analog Devices AD537. (This 
device may act as a temperature sensor by itself.) This is now 
used for a frequency source for the QBX-TMR as configured above. 



The measured 
period 
smal 1 
e.g. to 



output must: change 



slowly in relation to the gate 
of the frequency counter. In many applications only a 
portion of the full range is required for investigation, 
control water at a given temperature 30-35 degrees, while 
the sensor is capable of measuring from to 70 degrees. Feeding 
the full voltage into an A to D converter provides a loss of 
resolution. To get rid of the "common mode " voltage -30 
degrees is possible using a resistor bridge, but a variation in 
supply across the bridce leads to a change in voltage. This 
requires a fairly expensive solution of stabilised power supplies 
and calibration. Converting to a frequency side steps this 
problem, as the dynamic range is not as limited as an A to D 
converter. Afurther adventage is that this method of data 
transmission is far less susceptible to electrical noise. 

The QBX-TMR may also be used as a multichannel converter in 
combination with several voltage to frequency converters, with 
the channels under software control, allowing different source 
and gate inputs being fed into the counter. 



Reccomended 
application 



Rev : 1 . 



reading 
note . 



on the subject is the AD537 data sheet and 



B.l